/external/vboot_reference/firmware/stub/ |
H A D | utility_stub.c | 20 int Memcmp(const void *src1, const void *src2, size_t n) argument 22 return memcmp(src1, src2, n);
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/external/valgrind/none/tests/ppc32/ |
H A D | jm-insns.c | 6322 unsigned int *src1, *src2, *dst; local 6362 src1 = (unsigned int*)&vec_in1; 6367 printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]); 6388 unsigned int *src1, *src2, *src3, *dst; local 6431 src1 = (unsigned int*)&vec_in1; 6437 src1[0], src1[ 6463 unsigned int *src1, *src2, *dst; local 6533 unsigned int *src1, *dst; local 6661 unsigned int *src1, *src2, *dst; local 7088 unsigned int *src1, *src2, *dst; local 7155 unsigned int *src1, *src2, *src3, *dst; local [all...] |
/external/valgrind/none/tests/ppc64/ |
H A D | jm-insns.c | 6322 unsigned int *src1, *src2, *dst; local 6362 src1 = (unsigned int*)&vec_in1; 6367 printf("%08x%08x%08x%08x, ", src1[0], src1[1], src1[2], src1[3]); 6388 unsigned int *src1, *src2, *src3, *dst; local 6431 src1 = (unsigned int*)&vec_in1; 6437 src1[0], src1[ 6463 unsigned int *src1, *src2, *dst; local 6533 unsigned int *src1, *dst; local 6661 unsigned int *src1, *src2, *dst; local 7088 unsigned int *src1, *src2, *dst; local 7155 unsigned int *src1, *src2, *src3, *dst; local [all...] |
/external/valgrind/VEX/priv/ |
H A D | host_x86_isel.c | 1040 HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); local 1043 addInstr(env, mk_iMOVsd_RR(src1,dst));
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H A D | guest_ppc_toIR.c | 1669 static IRTemp gen_vpopcntd_mode32 ( IRTemp src1, IRTemp src2 ) argument 1689 old = src1; 4439 static IRExpr * CmpGT128U ( IRExpr *src1, IRExpr *src2 ) argument 4446 unop( Iop_V128HIto64, src1 ) ); 4448 unop( Iop_V128HIto64, src1 ), 4452 unop( Iop_V128to64, src1) ); 17329 static IRExpr * _get_maxmin_fp_cmp(IRTemp src1, IRTemp src2, Bool isMin) argument 17333 mkexpr( src1 ) ), 17340 /* then: use src1 */ 17341 mkexpr( src1 ), [all...] |
H A D | guest_s390_toIR.c | 7219 IRTemp src1 = newTemp(Ity_F32); local 7272 assign(src1, get_fpr_w0(4)); /* get source from FPR 4,6 */ 7273 s390_cc_thunk_putFZ(S390_CC_OP_PFPO_64, src1, gr0); 7296 /* get source from FPR 4,6 - already set in src1 */ 7297 assign(dst1, binop(Iop_F32toD32, irrm, mkexpr(src1))); 7300 s390_cc_thunk_putFZ(S390_CC_OP_PFPO_32, src1, gr0);
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H A D | host_amd64_isel.c | 1239 HReg src1 = iselIntExpr_R(env, e->Iex.Binop.arg1); local 1242 addInstr(env, mk_iMOVsd_RR(src1, dst));
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H A D | host_mips_defs.c | 1083 MIPSInstr *MIPSInstr_FpTernary ( MIPSFpOp op, HReg dst, HReg src1, HReg src2, argument 1090 i->Min.FpTernary.src1 = src1; 1451 ppHRegMIPS(i->Min.FpTernary.src1, mode64); 1745 addHRegUse(u, HRmRead, i->Min.FpTernary.src1); 1899 mapReg(m, &i->Min.FpTernary.src1); 3513 UInt fr_src1 = fregNo(i->Min.FpTernary.src1, mode64); 3521 UInt fr_src1 = dregNo(i->Min.FpTernary.src1); 3529 UInt fr_src1 = fregNo(i->Min.FpTernary.src1, mode64); 3537 UInt fr_src1 = dregNo(i->Min.FpTernary.src1); [all...] |
H A D | host_mips_defs.h | 550 HReg src1; member in struct:__anon28398::__anon28399::__anon28422 651 extern MIPSInstr *MIPSInstr_FpTernary ( MIPSFpOp op, HReg dst, HReg src1,
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H A D | host_mips_isel.c | 3342 HReg src1 = iselFltExpr(env, e->Iex.Qop.details->arg2); local 3347 src1, src2, src3)); 3603 HReg src1 = iselDblExpr(env, e->Iex.Qop.details->arg2); local 3608 src1, src2, src3));
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H A D | host_ppc_defs.c | 1517 HReg src1, HReg src2 ) { 1522 i->Pin.AvBCDV128Binary.src1 = src1; 2172 ppHRegPPC(i->Pin.AvBCDV128Binary.src1); 2660 addHRegUse(u, HRmRead, i->Pin.AvBCDV128Binary.src1); 3010 mapReg(m, &i->Pin.AvBCDV128Binary.src1); 5659 UInt v_src1 = vregEnc(i->Pin.AvBCDV128Binary.src1); 1516 PPCInstr_AvBCDV128Binary( PPCAvOp op, HReg dst, HReg src1, HReg src2 ) argument
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H A D | host_ppc_defs.h | 955 HReg src1; member in struct:__anon28460::__anon28461::__anon28515 1159 HReg src1, HReg src2 );
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H A D | host_s390_defs.c | 648 addHRegUse(u, HRmRead, insn->variant.compare.src1); 970 insn->variant.compare.src1 = lookupHRegRemap(m, insn->variant.compare.src1); 5550 s390_insn_compare(UChar size, HReg src1, s390_opnd_RMI src2, argument 5559 insn->variant.compare.src1 = src1; 6660 s390_sprintf(buf, "%M %R,%O", op, insn->variant.compare.src1, 8214 op1 = insn->variant.compare.src1;
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H A D | host_s390_defs.h | 442 HReg src1; member in struct:__anon28559::__anon28560::__anon28573
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H A D | guest_amd64_toIR.c | 19267 IRTemp src1 = newTemp(Ity_F32); local 19282 assign( src1, 19299 assign( src1, loadLE(Ity_F32, 19319 assign(res1, binop(Iop_RoundF32toInt, mkexpr(rm), mkexpr(src1)) ); 19337 IRTemp src1 = newTemp(Ity_F64); local 19348 assign( src1, 19361 assign( src1, loadLE(Ity_F64, 19377 assign(res1, binop(Iop_RoundF64toInt, mkexpr(rm), mkexpr(src1)) ); 29806 IRTemp src1 = newTemp(ty); local 29950 IRTemp src1 = newTemp(ty); local 30088 IRTemp src1 = newTemp(ty); local 30145 IRTemp src1 = newTemp(ty); local [all...] |
/external/v8/src/arm/ |
H A D | assembler-arm.cc | 1509 void Assembler::and_(Register dst, Register src1, const Operand& src2, argument 1511 addrmod1(cond | AND | s, src1, dst, src2); 1515 void Assembler::eor(Register dst, Register src1, const Operand& src2, argument 1517 addrmod1(cond | EOR | s, src1, dst, src2); 1521 void Assembler::sub(Register dst, Register src1, const Operand& src2, argument 1523 addrmod1(cond | SUB | s, src1, dst, src2); 1527 void Assembler::rsb(Register dst, Register src1, const Operand& src2, argument 1529 addrmod1(cond | RSB | s, src1, dst, src2); 1533 void Assembler::add(Register dst, Register src1, const Operand& src2, argument 1535 addrmod1(cond | ADD | s, src1, ds 1539 adc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1545 sbc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1551 rsc(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1557 tst(Register src1, const Operand& src2, Condition cond) argument 1562 teq(Register src1, const Operand& src2, Condition cond) argument 1567 cmp(Register src1, const Operand& src2, Condition cond) argument 1579 cmn(Register src1, const Operand& src2, Condition cond) argument 1584 orr(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1650 bic(Register dst, Register src1, const Operand& src2, SBit s, Condition cond) argument 1662 mla(Register dst, Register src1, Register src2, Register srcA, SBit s, Condition cond) argument 1670 mls(Register dst, Register src1, Register src2, Register srcA, Condition cond) argument 1679 sdiv(Register dst, Register src1, Register src2, Condition cond) argument 1688 udiv(Register dst, Register src1, Register src2, Condition cond) argument 1697 mul(Register dst, Register src1, Register src2, SBit s, Condition cond) argument 1705 smmla(Register dst, Register src1, Register src2, Register srcA, Condition cond) argument 1713 smmul(Register dst, Register src1, Register src2, Condition cond) argument 1721 smlal(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1734 smull(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1747 umlal(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1760 umull(Register dstL, Register dstH, Register src1, Register src2, SBit s, Condition cond) argument 1875 pkhbt(Register dst, Register src1, const Operand& src2, Condition cond ) argument 1894 pkhtb(Register dst, Register src1, const Operand& src2, Condition cond) argument 1926 sxtab(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 1952 sxtah(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 1978 uxtab(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 2016 uxtah(Register dst, Register src1, Register src2, int rotate, Condition cond) argument 2123 strd(Register src1, Register src2, const MemOperand& dst, Condition cond) argument 2139 strex(Register src1, Register src2, Register dst, Condition cond) argument 2155 strexb(Register src1, Register src2, Register dst, Condition cond) argument 2171 strexh(Register src1, Register src2, Register dst, Condition cond) argument 2891 vmov(const DwVfpRegister dst, const Register src1, const Register src2, const Condition cond) argument 3228 vadd(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3251 vadd(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3269 vsub(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3292 vsub(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3310 vmul(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3333 vmul(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3351 vmla(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3372 vmla(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3388 vmls(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3409 vmls(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3425 vdiv(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3448 vdiv(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3466 vcmp(const DwVfpRegister src1, const DwVfpRegister src2, const Condition cond) argument 3484 vcmp(const SwVfpRegister src1, const SwVfpRegister src2, const Condition cond) argument 3499 vcmp(const DwVfpRegister src1, const double src2, const Condition cond) argument 3514 vcmp(const SwVfpRegister src1, const float src2, const Condition cond) argument 3527 vmaxnm(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3543 vmaxnm(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 3559 vminnm(const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3575 vminnm(const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 3591 vsel(Condition cond, const DwVfpRegister dst, const DwVfpRegister src1, const DwVfpRegister src2) argument 3623 vsel(Condition cond, const SwVfpRegister dst, const SwVfpRegister src1, const SwVfpRegister src2) argument 4121 veor(DwVfpRegister dst, DwVfpRegister src1, DwVfpRegister src2) argument 4138 EncodeNeonBinaryBitwiseOp(BinaryBitwiseOp op, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4182 vand(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4190 vbsl(QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4198 veor(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4206 vorr(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4227 EncodeNeonBinOp(FPBinOp op, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4289 EncodeNeonBinOp(IntegerBinOp op, NeonDataType dt, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4344 EncodeNeonBinOp(IntegerBinOp op, NeonSize size, const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4353 vadd(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4361 vadd(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4369 vqadd(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4377 vsub(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4385 vsub(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4393 vqsub(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4401 vmul(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4409 vmul(NeonSize size, QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4417 vmin(const QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2) argument 4425 vmin(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4433 vmax(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4441 vmax(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4516 vrecps(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4524 vrsqrts(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4532 vtst(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4540 vceq(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4548 vceq(NeonSize size, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4556 vcge(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4564 vcge(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4572 vcgt(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4580 vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2) argument 4588 vext(QwNeonRegister dst, const QwNeonRegister src1, const QwNeonRegister src2, int bytes) argument [all...] |
H A D | assembler-arm.h | 808 void and_(Register dst, Register src1, const Operand& src2, 811 void eor(Register dst, Register src1, const Operand& src2, 814 void sub(Register dst, Register src1, const Operand& src2, 816 void sub(Register dst, Register src1, Register src2, 818 sub(dst, src1, Operand(src2), s, cond); 821 void rsb(Register dst, Register src1, const Operand& src2, 824 void add(Register dst, Register src1, const Operand& src2, 826 void add(Register dst, Register src1, Register src2, 828 add(dst, src1, Operand(src2), s, cond); 831 void adc(Register dst, Register src1, cons [all...] |
H A D | macro-assembler-arm.cc | 296 void MacroAssembler::Mls(Register dst, Register src1, Register src2, argument 300 mls(dst, src1, src2, srcA, cond); 303 mul(ip, src1, src2, LeaveCC, cond); 309 void MacroAssembler::And(Register dst, Register src1, const Operand& src2, argument 320 ubfx(dst, src1, 0, 323 and_(dst, src1, src2, LeaveCC, cond); 328 void MacroAssembler::Ubfx(Register dst, Register src1, int lsb, int width, argument 333 and_(dst, src1, Operand(mask), LeaveCC, cond); 339 ubfx(dst, src1, lsb, width, cond); 344 void MacroAssembler::Sbfx(Register dst, Register src1, in 3399 MovToFloatParameters(DwVfpRegister src1, DwVfpRegister src2) argument [all...] |
H A D | macro-assembler-arm.h | 152 void Mls(Register dst, Register src1, Register src2, Register srcA, 154 void And(Register dst, Register src1, const Operand& src2, 337 void Push(Register src1, Register src2, Condition cond = al) { argument 338 if (src1.code() > src2.code()) { 339 stm(db_w, sp, src1.bit() | src2.bit(), cond); 341 str(src1, MemOperand(sp, 4, NegPreIndex), cond); 347 void Push(Register src1, Register src2, Register src3, Condition cond = al) { argument 348 if (src1.code() > src2.code()) { 350 stm(db_w, sp, src1.bit() | src2.bit() | src3.bit(), cond); 352 stm(db_w, sp, src1 362 Push(Register src1, Register src2, Register src3, Register src4, Condition cond = al) argument 389 Push(Register src1, Register src2, Register src3, Register src4, Register src5, Condition cond = al) argument 418 Pop(Register src1, Register src2, Condition cond = al) argument 429 Pop(Register src1, Register src2, Register src3, Condition cond = al) argument 445 Pop(Register src1, Register src2, Register src3, Register src4, Condition cond = al) argument [all...] |
H A D | simulator-arm.cc | 4011 T src1[kLanes], src2[kLanes]; local 4012 simulator->get_q_register(Vn, src1); 4015 src1[i] = Clamp<T>(Widen(src1[i]) + Widen(src2[i])); 4017 simulator->set_q_register(Vd, src1); 4023 T src1[kLanes], src2[kLanes]; local 4024 simulator->get_q_register(Vn, src1); 4027 src1[i] = Clamp<T>(Widen(src1[i]) - Widen(src2[i])); 4029 simulator->set_q_register(Vd, src1); 4074 uint32_t src1[4]; local 4087 uint32_t src1[4], src2[4]; local 4128 int8_t src1[16], src2[16]; local 4141 int16_t src1[8], src2[8]; local 4154 int32_t src1[4], src2[4]; local 4178 int8_t src1[16], src2[16]; local 4191 int16_t src1[8], src2[8]; local 4204 int32_t src1[4], src2[4]; local 4229 uint8_t src1[16], src2[16]; local 4239 uint16_t src1[8], src2[8]; local 4249 uint32_t src1[4], src2[4]; local 4266 uint8_t src1[16], src2[16]; local 4276 uint16_t src1[8], src2[8]; local 4286 uint32_t src1[4], src2[4]; local 4308 uint8_t src1[16], src2[16]; local 4318 uint16_t src1[8], src2[8]; local 4328 uint32_t src1[4], src2[4]; local 4348 float src1[4], src2[4]; local 4369 float src1[4], src2[4]; local 4384 float src1[4], src2[4]; local 4450 uint8_t src1[16], src2[16], dst[16]; local 4582 uint32_t dst[4], src1[4], src2[4]; local 4593 uint64_t src1, src2; local 4601 uint32_t src1[4], src2[4]; local 4641 uint8_t src1[16], src2[16]; local 4654 uint16_t src1[8], src2[8]; local 4667 uint32_t src1[4], src2[4]; local 4691 uint8_t src1[16], src2[16]; local 4704 uint16_t src1[8], src2[8]; local 4717 uint32_t src1[4], src2[4]; local 4741 uint8_t src1[16], src2[16]; local 4751 uint16_t src1[8], src2[8]; local 4761 uint32_t src1[4], src2[4]; local 4779 uint8_t src1[16], src2[16]; local 4789 uint16_t src1[8], src2[8]; local 4799 uint32_t src1[4], src2[4]; local 4818 float src1[4], src2[4]; local 4834 float src1[4], src2[4]; local 4979 uint8_t src1[16], src2[16], dst1[16], dst2[16]; local 4993 uint16_t src1[8], src2[8], dst1[8], dst2[8]; local 5007 uint32_t src1[4], src2[4], dst1[4], dst2[4]; local [all...] |
/external/v8/src/arm64/ |
H A D | macro-assembler-arm64-inl.h | 1351 void MacroAssembler::SmiTagAndPush(Register src1, Register src2) { argument 1355 Push(src1.W(), wzr, src2.W(), wzr);
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H A D | macro-assembler-arm64.cc | 868 void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1, argument 870 DCHECK(AreSameSizeAndType(src0, src1, src2, src3)); 872 int count = 1 + src1.IsValid() + src2.IsValid() + src3.IsValid(); 876 PushHelper(count, size, src0, src1, src2, src3); 880 void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1, argument 884 DCHECK(AreSameSizeAndType(src0, src1, src2, src3, src4, src5, src6, src7)); 890 PushHelper(4, size, src0, src1, src2, src3); 930 void MacroAssembler::Push(const Register& src0, const FPRegister& src1) { argument 931 int size = src0.SizeInBytes() + src1.SizeInBytes(); 934 // Reserve room for src0 and push src1 1003 const CPURegister& src1 = registers.PopHighestIndex(); local 1115 PushHelper(int count, int size, const CPURegister& src0, const CPURegister& src1, const CPURegister& src2, const CPURegister& src3) argument 1260 PokePair(const CPURegister& src1, const CPURegister& src2, int offset) argument [all...] |
H A D | macro-assembler-arm64.h | 609 void Push(const CPURegister& src0, const CPURegister& src1 = NoReg, 611 void Push(const CPURegister& src0, const CPURegister& src1, 621 void Push(const Register& src0, const FPRegister& src1); 730 // Poke 'src1' and 'src2' onto the stack. The values written will be adjacent 731 // with 'src2' at a higher address than 'src1'. The offset is in bytes. 735 void PokePair(const CPURegister& src1, const CPURegister& src2, int offset); 979 inline void SmiTagAndPush(Register src1, Register src2); 1936 const CPURegister& src0, const CPURegister& src1,
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/external/v8/src/compiler/ia32/ |
H A D | code-generator-ia32.cc | 2579 Operand src1 = g.ToOperand(source); local 2580 __ push(src1); 2618 Operand src1 = g.HighOperand(source); local 2623 __ push(src1);
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/external/v8/src/compiler/mips/ |
H A D | code-generator-mips.cc | 276 ool_name(CodeGenerator* gen, T dst, T src1, T src2) \ 277 : OutOfLineCode(gen), dst_(dst), src1_(src1), src2_(src2) {} \ 1249 FPURegister src1 = i.InputSingleRegister(0); local 1251 auto ool = new (zone()) OutOfLineFloat32Max(this, dst, src1, src2); 1252 __ Float32Max(dst, src1, src2, ool->entry()); 1258 DoubleRegister src1 = i.InputDoubleRegister(0); local 1260 auto ool = new (zone()) OutOfLineFloat64Max(this, dst, src1, src2); 1261 __ Float64Max(dst, src1, src2, ool->entry()); 1267 FPURegister src1 = i.InputSingleRegister(0); local 1269 auto ool = new (zone()) OutOfLineFloat32Min(this, dst, src1, src 1276 DoubleRegister src1 = i.InputDoubleRegister(0); local [all...] |