Searched refs:Bit (Results 1 - 25 of 85) sorted by relevance

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/external/clang/test/Parser/
H A DMicrosoftExtensionsInlineAsm.c5 void __forceinline InterlockedBitTestAndSet (long *Base, long Bit) argument
8 mov eax, Bit
/external/v8/src/arm/
H A Dconstants-arm.h155 BIC = 14 << 21, // Bit Clear.
289 // Bit encoding P U W.
301 // Bit encoding P U W .
362 // standard SoftwareInterrupCode. Bit 23 is reserved for the stop feature.
484 inline int Bit(int nr) const { function in class:v8::internal::Instruction
503 static inline int Bit(Instr instr, int nr) { function in class:v8::internal::Instruction
553 inline int NValue() const { return Bit(7); }
554 inline int MValue() const { return Bit(5); }
555 inline int DValue() const { return Bit(22); }
557 inline int PValue() const { return Bit(2
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H A Dconstants-arm.cc23 high16 |= (0xff * Bit(18)) << 6; // xxbbbbbb,bbxxxxxx.
24 high16 |= (Bit(18) ^ 1) << 14; // xBxxxxxx,xxxxxxxx.
25 high16 |= Bit(19) << 15; // axxxxxxx,xxxxxxxx.
H A Dsimulator-arm.cc1400 if (instr->Bit(4) == 0) {
2097 if (instr->Bit(24) == 0) {
2105 if (instr->Bit(23) == 0) {
2106 if (instr->Bit(21) == 0) {
2120 if (instr->Bit(22) == 0) {
2151 if (instr->Bit(22) == 1) {
2173 if (instr->Bit(20) == 1) {
2245 if (instr->Bit(22) == 0) {
2333 if (((instr->Bits(7, 4) & 0xd) == 0xd) && (instr->Bit(20) == 0)) {
2745 if (instr->Bit(
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H A Ddisasm-arm.cc242 shift_names[instr->Bit(6) * 2],
366 (instr->Bit(24) == 0x0) &&
368 (instr->Bit(4) == 0x1)) {
370 reg = instr->Bits(19, 16) | (instr->Bit(7) << 4);
453 if (instr->Bit(21) == 0) {
479 if (instr->Bit(21) == 0) {
529 if ((instr->Bits(27, 25) == 0) && (instr->Bit(20) == 0) &&
530 (instr->Bits(7, 6) == 3) && (instr->Bit(4) == 1)) {
531 if (instr->Bit(5) == 1) {
623 if (instr->Bit(2
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/external/v8/src/arm64/
H A Ddecoder-arm64-inl.h102 DCHECK(instr->Bit(28) == 0x1);
122 if (instr->Bit(25) == 0) {
130 if (instr->Bit(25) == 0) {
131 if ((instr->Bit(24) == 0x1) ||
143 if (instr->Bit(25) == 0) {
144 if (instr->Bit(24) == 0) {
187 if ((instr->Bit(24) == 0x1) ||
216 if (instr->Bit(24) == 0) {
217 if (instr->Bit(28) == 0) {
218 if (instr->Bit(2
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/external/capstone/arch/X86/
H A DX86GenRegisterInfo.inc642 // GR8 Bit set.
652 // GR8_NOREX Bit set.
662 // GR8_ABCD_H Bit set.
672 // GR8_ABCD_L Bit set.
682 // GR16 Bit set.
692 // GR16_NOREX Bit set.
702 // VK1 Bit set.
712 // VK16 Bit set.
722 // VK2 Bit set.
732 // VK4 Bit se
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/external/capstone/arch/ARM/
H A DARMGenRegisterInfo.inc1183 // SPR Bit set.
1193 // GPR Bit set.
1203 // GPRwithAPSR Bit set.
1213 // SPR_8 Bit set.
1223 // GPRnopc Bit set.
1233 // rGPR Bit set.
1243 // hGPR Bit set.
1253 // tGPR Bit set.
1263 // GPRnopc_and_hGPR Bit set.
1273 // hGPR_and_rGPR Bit se
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/external/capstone/arch/SystemZ/
H A DSystemZGenRegisterInfo.inc320 // GRX32Bit Bit set.
330 // FP32Bit Bit set.
340 // GR32Bit Bit set.
350 // GRH32Bit Bit set.
360 // ADDR32Bit Bit set.
370 // CCRegs Bit set.
380 // FP64Bit Bit set.
390 // GR64Bit Bit set.
400 // ADDR64Bit Bit set.
410 // FP128Bit Bit se
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/external/capstone/arch/XCore/
H A DXCoreGenRegisterInfo.inc90 // RRegs Bit set.
100 // GRRegs Bit set.
/external/capstone/arch/Sparc/
H A DSparcGenRegisterInfo.inc376 // FCCRegs Bit set.
386 // FPRegs Bit set.
396 // IntRegs Bit set.
406 // DFPRegs Bit set.
416 // I64Regs Bit set.
426 // DFPRegs_with_sub_even Bit set.
436 // QFPRegs Bit set.
446 // QFPRegs_with_sub_even Bit set.
/external/capstone/arch/Mips/
H A DMipsGenRegisterInfo.inc1001 // OddSP Bit set.
1011 // CCR Bit set.
1021 // COP2 Bit set.
1031 // COP3 Bit set.
1041 // DSPR Bit set.
1051 // FGR32 Bit set.
1061 // FGRCC Bit set.
1071 // FGRH32 Bit set.
1081 // GPR32 Bit set.
1091 // HWRegs Bit se
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/external/capstone/arch/PowerPC/
H A DPPCGenRegisterInfo.inc688 // GPRC Bit set.
698 // GPRC_NOR0 Bit set.
708 // GPRC_and_GPRC_NOR0 Bit set.
718 // CRBITRC Bit set.
728 // F4RC Bit set.
738 // CRRC Bit set.
748 // CARRYRC Bit set.
758 // CCRC Bit set.
768 // CTRRC Bit set.
778 // VRSAVERC Bit se
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/external/capstone/arch/AArch64/
H A DAArch64GenRegisterInfo.inc1069 // FPR8 Bit set.
1079 // FPR16 Bit set.
1089 // GPR32all Bit set.
1099 // FPR32 Bit set.
1109 // GPR32 Bit set.
1119 // GPR32sp Bit set.
1129 // GPR32common Bit set.
1139 // CCR Bit set.
1149 // GPR32sponly Bit set.
1159 // GPR64all Bit se
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/external/v8/src/ppc/
H A Dsimulator-ppc.cc1618 if (instr->Bit(0) == 1) { // LK flag set
1692 if (instr->Bit(0)) { // RC bit set
1706 if (instr->Bit(0)) { // RC bit set
1774 if (instr->Bit(0)) { // RC bit set
1788 if (instr->Bit(0)) { // RC bit set
1801 if (instr->Bit(0)) { // RC bit set
1814 if (instr->Bit(0)) { // RC bit set
1827 if (instr->Bit(0)) { // RC bit set
1839 if (instr->Bit(0)) { // RC bit set
1958 int sh = (instr->Bits(15, 11) | (instr->Bit(
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H A Ddisasm-ppc.cc206 if (instr->Bit(10) == 1) {
212 if (instr->Bit(0) == 1) {
236 // Link (LK) Bit 0
237 if (instr->Bit(0) == 1) {
243 // Absolute Address Bit 1
244 if (instr->Bit(1) == 1) {
281 value = (sh | (instr->Bit(1) << 5));
297 value = (instr->Bits(10, 6) | (instr->Bit(5) << 5));
305 value = (instr->Bits(10, 6) | (instr->Bit(5) << 5));
484 if (instr->Bit(
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/external/syslinux/core/
H A Dpxeisr.inc169 pxe_need_poll resb 1 ; Bit 0 = need polling
170 ; Bit 1 = polling active
/external/llvm/include/llvm/TableGen/
H A DRecord.h366 virtual Init *getBit(unsigned Bit) const = 0;
441 Init *getBit(unsigned Bit) const override {
468 Init *getBit(unsigned Bit) const override {
469 assert(Bit < 1 && "Bit index out of range!");
528 Init *getBit(unsigned Bit) const override {
529 assert(Bit < NumBits && "Bit index out of range!");
530 return getTrailingObjects<Init *>()[Bit];
567 Init *getBit(unsigned Bit) cons
958 unsigned Bit; member in class:llvm::VarBitInit
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/external/llvm/lib/Transforms/IPO/
H A DLowerTypeTests.cpp179 unsigned Bit = 0; local
181 if (BitAllocs[I] < BitAllocs[Bit])
182 Bit = I;
184 AllocByteOffset = BitAllocs[Bit];
188 BitAllocs[Bit] = ReqSize;
193 AllocMask = 1 << Bit;
392 for (auto Bit : BSI.Bits)
393 Bits |= uint64_t(1) << Bit;
479 Value *Bit = createBitSetTest(ThenB, BSI, BAI, BitOffset); local
487 P->addIncoming(Bit, Then
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/external/llvm/lib/DebugInfo/DWARF/
H A DDWARFDebugInfoEntry.cpp85 uint64_t Bit = 1ULL << Shift;
86 if (const char *PropName = ApplePropertyString(Bit))
89 OS << format("DW_APPLE_PROPERTY_0x%" PRIx64, Bit);
90 if (!(Val ^= Bit))
/external/llvm/lib/TableGen/
H A DTGLexer.h46 Bit, Bits, Class, Code, Dag, Def, Foreach, Defm, Field, In, Int, Let, List, enumerator in enum:llvm::tgtok::TokKind
/external/swiftshader/third_party/LLVM/include/llvm/TableGen/
H A DRecord.h604 unsigned Bit) const = 0;
672 Init *getBit(unsigned Bit) const {
673 assert(Bit < Bits.size() && "Bit index out of range!");
674 return Bits[Bit];
727 unsigned Bit) const {
771 unsigned Bit) const {
863 unsigned Bit) const {
901 unsigned Bit) const;
1080 unsigned Bit) cons
1103 unsigned Bit; member in class:llvm::VarBitInit
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/external/swiftshader/third_party/LLVM/lib/TableGen/
H A DTGLexer.h44 Bit, Bits, Class, Code, Dag, Def, Defm, Field, In, Int, Let, List, enumerator in enum:llvm::tgtok::TokKind
/external/llvm/lib/Fuzzer/
H A DFuzzerMutate.cpp53 int Bit = Rand(8); local
54 char Mask = 1 << Bit;
56 if (X & (1 << Bit))
/external/swiftshader/third_party/subzero/pnacl-llvm/
H A DNaClBitstreamReader.cpp28 std::string llvm::naclbitc::getBitAddress(uint64_t Bit) { argument
31 Stream << (Bit / 8) << ":" << (Bit % 8);

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