| /external/kernel-headers/original/uapi/asm-generic/ |
| H A D | termbits.h | 94 #define CR2 0002000 macro
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| /external/kernel-headers/original/uapi/asm-mips/asm/ |
| H A D | termbits.h | 114 #define CR2 0002000 macro
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
| H A D | PPCBaseInfo.h | 33 case R2 : case X2 : case F2 : case V2 : case CR2: case CR0EQ: return 2;
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.h | 36 Reg = PPC::CR2;
|
| H A D | PPCFrameLowering.cpp | 156 // to the slot for CR2, which is the first of the nonvolatile CR
159 {PPC::CR2, -4},
1063 // subregisters of CR2. We just need to emit a move of CR2.
1069 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
1075 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1076 // In the ELFv1 ABI, only CR2 is noted in CFI and stands in for
1079 unsigned CRReg = isELFv2ABI? Reg : (unsigned) PPC::CR2;
1433 (SavedRegs.test(PPC::CR2) ||
1619 // Only CR2 (th
[all...] |
| H A D | PPCRegisterInfo.cpp | 727 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
732 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
|
| /external/python/cpython2/Modules/ |
| H A D | termios.c | 450 #ifdef CR2
451 {"CR2", CR2},
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| /external/python/cpython3/Modules/ |
| H A D | termios.c | 480 #ifdef CR2
481 {"CR2", CR2},
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| /external/python/cpython2/Lib/plat-irix5/ |
| H A D | IOCTL.py | 109 CR2 = 0002000 variable
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| /external/python/cpython2/Lib/plat-irix6/ |
| H A D | IOCTL.py | 109 CR2 = 0002000 variable
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCRegisterInfo.cpp | 118 PPC::CR2, PPC::CR3, PPC::CR4,
144 PPC::CR2, PPC::CR3, PPC::CR4,
172 PPC::CR2, PPC::CR3, PPC::CR4,
198 PPC::CR2, PPC::CR3, PPC::CR4,
|
| H A D | PPCInstrInfo.cpp | 431 Reg = PPC::CR2;
560 Reg = PPC::CR2;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/InstPrinter/ |
| H A D | PPCInstPrinter.cpp | 181 case PPC::CR2: RegNo = 2; break;
|
| /external/llvm/lib/Target/PowerPC/InstPrinter/ |
| H A D | PPCInstPrinter.cpp | 363 case PPC::CR2: RegNo = 2; break;
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 263 ENTRY(CR2) \
|
| /external/capstone/arch/X86/ |
| H A D | X86DisassemblerDecoder.h | 363 ENTRY(CR2) \
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| H A D | X86DisassemblerDecoder.h | 357 ENTRY(CR2) \
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/ |
| H A D | X86MCTargetDesc.cpp | 213 case X86::CR2: case X86::CR10: case X86::DR2: return 2;
|
| /external/toybox/toys/pending/ |
| H A D | stty.c | 105 { "cr2", CR2, CRDLY }, { "cr3", CR3, CRDLY }, { "tab0", TAB0, TABDLY },
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| H A D | X86GenRegisterInfo.inc | 32 CR2 = 13,
261 const unsigned CR2_Overlaps[] = { X86::CR2, 0 };
578 { "CR2", CR2_Overlaps, Empty_SubRegsSet, Empty_SuperRegsSet },
800 X86::CR0, X86::CR1, X86::CR2, X86::CR3, X86::CR4, X86::CR5, X86::CR6, X86::CR7, X86::CR8, X86::CR9, X86::CR10, X86::CR11, X86::CR12, X86::CR13, X86::CR14, X86::CR15,
1445 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, false );
1606 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, false );
1767 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, false );
1933 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, true );
2094 RI->mapLLVMRegToDwarfReg(X86::CR2, -1, true );
2255 RI->mapLLVMRegToDwarfReg(X86::CR2,
[all...] |
| H A D | X86GenAsmWriter.inc | 6684 case X86::CR2:
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| H A D | X86GenAsmWriter1.inc | 7427 case X86::CR2:
|
| /external/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 66 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
|
| /external/llvm/lib/Target/PowerPC/AsmParser/ |
| H A D | PPCAsmParser.cpp | 174 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
|
| /external/mesa3d/src/mesa/x86/ |
| H A D | assyntax.h | 126 #define CR2 cr2 macro
188 #define CR2 %cr2 macro
|