| /external/v8/src/regexp/arm64/ |
| H A D | regexp-macro-assembler-arm64.cc | 289 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits);
450 __ Lsr(x11, GetCachedRegister(start_reg), kWRegSizeInBits);
878 __ Lsr(capture_end.X(), capture_start.X(), kWRegSizeInBits);
1200 __ Lsr(current_input_offset().X(), cached_register, kWRegSizeInBits);
1515 __ Lsr(maybe_result.X(), GetCachedRegister(register_index),
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| /external/vixl/test/aarch32/ |
| H A D | test-disasm-a32.cc | 3461 COMPARE_T32(Lsr(eq, r0, r1, 16),
3465 COMPARE_T32(Lsr(eq, r0, r1, 32),
3469 COMPARE_T32(Lsr(eq, r0, r1, 0),
3475 COMPARE_T32(Lsr(eq, r7, r7, r3),
3479 COMPARE_T32(Lsr(eq, r8, r8, r3),
4061 CHECK_T32_16(Lsr(DontCare, r0, r1, 32), "lsrs r0, r1, #32\n");
4063 CHECK_T32_16_IT_BLOCK(Lsr(DontCare, eq, r0, r1, 32),
4067 CHECK_T32_16(Lsr(DontCare, r0, r0, r1), "lsrs r0, r1\n");
4069 CHECK_T32_16_IT_BLOCK(Lsr(DontCare, eq, r0, r0, r1),
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| H A D | test-simulator-cond-rd-rn-operand-rm-a32.cc | 146 M(Lsr) \
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| H A D | test-simulator-cond-rd-rn-operand-rm-t32.cc | 146 M(Lsr) \
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| H A D | test-assembler-aarch32.cc | 784 __ Lsr(r4, r1, 8);
810 __ Lsr(r4, r1, r9);
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| /external/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineInternal.h | 528 Value *SimplifyShrShlDemandedBits(Instruction *Lsr, Instruction *Sftl,
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| /external/v8/src/compiler/arm64/ |
| H A D | code-generator-arm64.cc | 1127 ASSEMBLE_SHIFT(Lsr, 64);
1130 ASSEMBLE_SHIFT(Lsr, 32);
1489 __ Lsr(i.OutputRegister(), i.OutputRegister(), 32);
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| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| H A D | assembler_arm.h | 1054 void Lsr(Register rd, Register rm, const Operand& shift_imm,
1057 void Lsr(Register rd, Register rm, Register rs, Condition cond = AL);
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| H A D | assembler_arm.cc | 2615 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
2619 ASSERT(shift != 0); // Do not use Lsr if no shift is wanted.
2627 void Assembler::Lsr(Register rd, Register rm, Register rs, Condition cond) {
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| /external/v8/src/arm64/ |
| H A D | macro-assembler-arm64-inl.h | 919 void MacroAssembler::Lsr(const Register& rd, function in class:v8::internal::MacroAssembler
928 void MacroAssembler::Lsr(const Register& rd, function in class:v8::internal::MacroAssembler
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| H A D | macro-assembler-arm64.h | 488 inline void Lsr(const Register& rd, const Register& rn, unsigned shift);
489 inline void Lsr(const Register& rd, const Register& rn, const Register& rm);
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| H A D | macro-assembler-arm64.cc | 3994 Lsr(bitmap_scratch, bitmap_scratch, shift_scratch);
4049 Lsr(load_scratch, load_scratch, shift_scratch);
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| H A D | code-stubs-arm64.cc | 758 __ Lsr(exponent_abs, exponent_abs, 1);
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| /external/swiftshader/third_party/subzero/src/ |
| H A D | IceInstARM32.h | 399 Lsr, enumerator in enum:Ice::ARM32::InstARM32::InstKindARM32
1010 using InstARM32Lsr = InstARM32ThreeAddrGPR<InstARM32::Lsr>;
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| H A D | IceInstARM32.cpp | 3490 template class InstARM32ThreeAddrGPR<InstARM32::Lsr>;
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| /external/v8/src/crankshaft/arm64/ |
| H A D | lithium-codegen-arm64.cc | 4492 __ Lsr(result, left, right);
4514 case Token::SHR: __ Lsr(result, left, shift_count); break;
4554 __ Lsr(result, left, result);
4587 __ Lsr(result, left, shift_count);
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| /external/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.h | 1617 void Lsr(const Register& rd, const Register& rn, unsigned shift) { function in class:vixl::aarch64::MacroAssembler
1624 void Lsr(const Register& rd, const Register& rn, const Register& rm) { function in class:vixl::aarch64::MacroAssembler
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| /external/vixl/src/aarch32/ |
| H A D | macro-assembler-aarch32.h | 2318 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) { function in class:vixl::aarch32::MacroAssembler
2335 void Lsr(Register rd, Register rm, const Operand& operand) { function in class:vixl::aarch32::MacroAssembler
2336 Lsr(al, rd, rm, operand);
2338 void Lsr(FlagsUpdate flags, function in class:vixl::aarch32::MacroAssembler
2345 Lsr(cond, rd, rm, operand);
2359 Lsr(cond, rd, rm, operand);
2364 void Lsr(FlagsUpdate flags, function in class:vixl::aarch32::MacroAssembler
2368 Lsr(flags, al, rd, rm, operand);
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| /external/vixl/test/aarch64/ |
| H A D | test-assembler-aarch64.cc | 9505 __ Lsr(x16, x0, x1);
9506 __ Lsr(x17, x0, x2);
9507 __ Lsr(x18, x0, x3);
9508 __ Lsr(x19, x0, x4);
9509 __ Lsr(x20, x0, x5);
9510 __ Lsr(x21, x0, x6);
9512 __ Lsr(w22, w0, w1);
9513 __ Lsr(w23, w0, w2);
9514 __ Lsr(w24, w0, w3);
9515 __ Lsr(w2
[all...] |
| /external/v8/src/builtins/arm64/ |
| H A D | builtins-arm64.cc | 1110 __ Lsr(x11, x11, kPointerSizeLog2);
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| /external/v8/src/full-codegen/arm64/ |
| H A D | full-codegen-arm64.cc | 1547 __ Lsr(x10, left, right);
|