/external/swiftshader/third_party/subzero/pydir/ |
H A D | gen_arm32_reg_tables.py | 60 class Reg(object): class in inherits:object 82 Reg( 'r0', 0, IsScratch=1, CCArg=1, IsGPR = 1, IsInt=1, Aliases= 'r0, r0r1'), 83 Reg( 'r1', 1, IsScratch=1, CCArg=2, IsGPR = 1, IsInt=1, Aliases= 'r1, r0r1'), 84 Reg( 'r2', 2, IsScratch=1, CCArg=3, IsGPR = 1, IsInt=1, Aliases= 'r2, r2r3'), 85 Reg( 'r3', 3, IsScratch=1, CCArg=4, IsGPR = 1, IsInt=1, Aliases= 'r3, r2r3'), 86 Reg( 'r4', 4, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r4, r4r5'), 87 Reg( 'r5', 5, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r5, r4r5'), 88 Reg( 'r6', 6, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r6, r6r7'), 89 Reg( 'r7', 7, IsPreserved=1, IsGPR = 1, IsInt=1, Aliases= 'r7, r6r7'), 90 Reg( 'r [all...] |
/external/clang/lib/StaticAnalyzer/Core/ |
H A D | DynamicTypeMap.cpp | 22 const MemRegion *Reg) { 23 Reg = Reg->StripCasts(); 26 const DynamicTypeInfo *GDMType = State->get<DynamicTypeMap>(Reg); 31 if (const TypedRegion *TR = dyn_cast<TypedRegion>(Reg)) 34 if (const SymbolicRegion *SR = dyn_cast<SymbolicRegion>(Reg)) { 42 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg, argument 44 Reg = Reg->StripCasts(); 45 ProgramStateRef NewState = State->set<DynamicTypeMap>(Reg, NewT 21 getDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg) argument [all...] |
/external/llvm/lib/Target/WebAssembly/ |
H A D | WebAssemblyMachineFunctionInfo.cpp | 23 unsigned Reg = UnusedReg; local 24 WARegs.resize(MF.getRegInfo().getNumVirtRegs(), Reg);
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H A D | WebAssemblyMachineFunctionInfo.h | 58 void setVarargBufferVreg(unsigned Reg) { VarargVreg = Reg; } argument 79 unsigned getWAReg(unsigned Reg) const { 80 assert(TargetRegisterInfo::virtReg2Index(Reg) < WARegs.size()); 81 return WARegs[TargetRegisterInfo::virtReg2Index(Reg)]; 85 static unsigned getWARegStackId(unsigned Reg) { argument 86 assert(Reg & INT32_MIN); 87 return Reg & INT32_MAX;
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZMachineFunctionInfo.h | 43 void setLowReg(unsigned Reg) { LowReg = Reg; } argument 46 void setHighReg(unsigned Reg) { HighReg = Reg; } argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonRDF.cpp | 23 if (TargetRegisterInfo::isVirtualRegister(RA.Reg) && 24 TargetRegisterInfo::isVirtualRegister(RB.Reg)) { 26 if (RA.Reg == RB.Reg) { 42 if (!TargetRegisterInfo::isPhysicalRegister(RR.Reg)) { 43 assert(TargetRegisterInfo::isVirtualRegister(RR.Reg)); 45 bool HasLo = RRs.count({RR.Reg, Hexagon::subreg_loreg}); 46 bool HasHi = RRs.count({RR.Reg, Hexagon::subreg_hireg}); 53 unsigned Lo = TRI.getSubReg(RR.Reg, Hexagon::subreg_loreg); 54 unsigned Hi = TRI.getSubReg(RR.Reg, Hexago [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 39 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument 41 VRegInfo[Reg].first = RC; 44 void MachineRegisterInfo::setRegBank(unsigned Reg, argument 46 VRegInfo[Reg].first = &RegBank; 50 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument 53 const TargetRegisterClass *OldRC = getRegClass(Reg); 62 setRegClass(Reg, NewRC); 67 MachineRegisterInfo::recomputeRegClass(unsigned Reg) { argument 69 const TargetRegisterClass *OldRC = getRegClass(Reg); 78 for (MachineOperand &MO : reg_nodbg_operands(Reg)) { 101 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); local 125 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); local 140 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local [all...] |
H A D | LivePhysRegs.cpp | 51 unsigned Reg = O->getReg(); local 52 if (Reg == 0) 54 removeReg(Reg); 63 unsigned Reg = O->getReg(); local 64 if (Reg == 0) 66 addReg(Reg); 79 unsigned Reg = O->getReg(); local 80 if (Reg == 0) 85 Clobbers.push_back(std::make_pair(Reg, &*O)); 90 removeReg(Reg); [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86MachineFunctionInfo.cpp | 25 unsigned Reg = *CSR; 28 if (X86::GR64RegClass.contains(Reg) || X86::GR32RegClass.contains(Reg))
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/external/capstone/arch/SystemZ/ |
H A D | SystemZMCTargetDesc.h | 32 unsigned SystemZMC_getFirstReg(unsigned Reg);
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/external/clang/include/clang/StaticAnalyzer/Core/PathSensitive/ |
H A D | DynamicTypeMap.h | 40 const MemRegion *Reg); 43 ProgramStateRef setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg, 48 const MemRegion *Reg, QualType NewTy, 50 return setDynamicTypeInfo(State, Reg, 47 setDynamicTypeInfo(ProgramStateRef State, const MemRegion *Reg, QualType NewTy, bool CanBeSubClassed = true) argument
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcMachineFunctionInfo.h | 43 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument 49 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
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/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
H A D | SystemZMCTargetDesc.h | 59 unsigned getFirstReg(unsigned Reg); 62 inline unsigned getRegAsGR64(unsigned Reg) { argument 63 return GR64Regs[getFirstReg(Reg)]; 67 inline unsigned getRegAsGR32(unsigned Reg) { argument 68 return GR32Regs[getFirstReg(Reg)]; 72 inline unsigned getRegAsGRH32(unsigned Reg) { argument 73 return GRH32Regs[getFirstReg(Reg)]; 77 inline unsigned getRegAsVR128(unsigned Reg) { argument 78 return VR128Regs[getFirstReg(Reg)];
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
H A D | AlphaMachineFunctionInfo.h | 48 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument 51 void setGlobalRetAddr(unsigned Reg) { GlobalRetAddr = Reg; } argument
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/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
H A D | PTXMachineFunctionInfo.h | 82 void addRetReg(unsigned Reg) { argument 83 if (!RegRets.count(Reg)) { 84 RegRets.insert(Reg); 88 RegNames[Reg] = name; 93 void addArgReg(unsigned Reg) { argument 94 RegArgs.insert(Reg); 98 RegNames[Reg] = name; 103 void addVirtualRegister(const TargetRegisterClass *TRC, unsigned Reg) { argument 107 if (!RegRets.count(Reg) && !RegArgs.count(Reg)) { [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
H A D | SparcMachineFunctionInfo.h | 37 void setGlobalBaseReg(unsigned Reg) { GlobalBaseReg = Reg; } argument 43 void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; } argument
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/external/llvm/include/llvm/MC/ |
H A D | MCWin64EH.h | 27 static WinEH::Instruction PushNonVol(MCSymbol *L, unsigned Reg) { argument 28 return WinEH::Instruction(Win64EH::UOP_PushNonVol, L, Reg, -1); 37 static WinEH::Instruction SaveNonVol(MCSymbol *L, unsigned Reg, argument 41 L, Reg, Offset); 43 static WinEH::Instruction SaveXMM(MCSymbol *L, unsigned Reg, argument 47 L, Reg, Offset); 49 static WinEH::Instruction SetFPReg(MCSymbol *L, unsigned Reg, unsigned Off) { argument 50 return WinEH::Instruction(UOP_SetFPReg, L, Reg, Off);
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/external/llvm/test/MC/Lanai/ |
H A D | memory.s | 10 ! CHECK-NEXT: <MCOperand Reg:13> 11 ! CHECK-NEXT: <MCOperand Reg:14> 18 ! CHECK-NEXT: <MCOperand Reg:13> 19 ! CHECK-NEXT: <MCOperand Reg:13> 26 ! CHECK-NEXT: <MCOperand Reg:13> 27 ! CHECK-NEXT: <MCOperand Reg:14> 34 ! CHECK-NEXT: <MCOperand Reg:13> 35 ! CHECK-NEXT: <MCOperand Reg:14> 42 ! CHECK-NEXT: <MCOperand Reg:13> 43 ! CHECK-NEXT: <MCOperand Reg [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | RegisterScavenging.h | 126 void setUsed(unsigned Reg); 129 bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); } 133 bool isUsed(unsigned Reg) const { return !RegsAvailable.test(Reg); } 134 bool isUnused(unsigned Reg) const { return RegsAvailable.test(Reg); } 136 /// isAliasUsed - Is Reg or an alias currently in use? 137 bool isAliasUsed(unsigned Reg) const; 148 /// Add Reg an [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | MachineRegisterInfo.cpp | 46 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { argument 47 VRegInfo[Reg].first = RC; 51 MachineRegisterInfo::constrainRegClass(unsigned Reg, argument 54 const TargetRegisterClass *OldRC = getRegClass(Reg); 62 setRegClass(Reg, NewRC); 67 MachineRegisterInfo::recomputeRegClass(unsigned Reg, const TargetMachine &TM) { argument 69 const TargetRegisterClass *OldRC = getRegClass(Reg); 77 for (reg_nodbg_iterator I = reg_nodbg_begin(Reg), E = reg_nodbg_end(); I != E; 89 setRegClass(Reg, NewRC); 103 unsigned Reg local 125 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); local [all...] |
H A D | DeadMachineInstructionElim.cpp | 72 unsigned Reg = MO.getReg(); local 73 if (TargetRegisterInfo::isPhysicalRegister(Reg) ? 74 LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) { 108 unsigned Reg = *LOI; local 109 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 110 LivePhysRegs.set(Reg); 138 unsigned Reg = MO.getReg(); local 139 if (!TargetRegisterInfo::isVirtualRegister(Reg)) 142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), 166 unsigned Reg = MO.getReg(); local 183 unsigned Reg = MO.getReg(); local [all...] |
H A D | AggressiveAntiDepBreaker.cpp | 61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { argument 62 unsigned Node = GroupNodeIndices[Reg]; 74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { 75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) 76 Regs.push_back(Reg); 83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!"); 96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) argument 107 IsLive(unsigned Reg) argument 190 unsigned Reg = *I; local [all...] |
H A D | CriticalAntiDepBreaker.cpp | 64 unsigned Reg = *I; local 65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 66 KillIndices[Reg] = BB->size(); 67 DefIndices[Reg] = ~0u; 70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { 86 unsigned Reg = *I; local 87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); 88 KillIndices[Reg] = BB->size(); 89 DefIndices[Reg] = ~0u; 92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alia 106 unsigned Reg = *I; local 205 unsigned Reg = MO.getReg(); local 257 unsigned Reg = MO.getReg(); local 292 unsigned Reg = MO.getReg(); local 586 unsigned Reg = MO.getReg(); local [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | LivePhysRegs.h | 74 void addReg(unsigned Reg) { argument 76 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); 77 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true); 84 void removeReg(unsigned Reg) { argument 86 assert(Reg <= TRI->getNumRegs() && "Expected a physical register."); 87 for (MCRegAliasIterator R(Reg, TRI, true); R.isValid(); ++R) 95 /// \brief Returns true if register @p Reg is contained in the set. This also 96 /// works if only the super register of @p Reg has been defined, because 100 bool contains(unsigned Reg) const { return LiveRegs.count(Reg); } [all...] |
/external/capstone/ |
H A D | MCRegisterInfo.c | 86 unsigned MCRegisterInfo_getMatchingSuperReg(MCRegisterInfo *RI, unsigned Reg, unsigned SubIdx, MCRegisterClass *RC) argument 90 if (Reg >= RI->NumRegs) { 94 DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SuperRegs); 99 if (MCRegisterClass_contains(RC, val) && Reg == MCRegisterInfo_getSubReg(RI, val, SubIdx)) 108 unsigned MCRegisterInfo_getSubReg(MCRegisterInfo *RI, unsigned Reg, unsigned Idx) argument 111 uint16_t *SRI = RI->SubRegIndices + RI->Desc[Reg].SubRegIndices; 113 DiffListIterator_init(&iter, (MCPhysReg)Reg, RI->DiffLists + RI->Desc[Reg].SubRegs); 134 bool MCRegisterClass_contains(MCRegisterClass *c, unsigned Reg) argument [all...] |