| /external/llvm/lib/CodeGen/ |
| H A D | AllocationOrder.cpp | 32 const RegisterClassInfo &RegClassInfo,
37 Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
30 AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo, const LiveRegMatrix *Matrix) argument
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| H A D | AllocationOrder.h | 38 /// @param RegClassInfo Information about reserved and allocatable registers.
41 const RegisterClassInfo &RegClassInfo,
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| H A D | RegAllocBase.cpp | 63 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
128 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
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| H A D | CriticalAntiDepBreaker.h | 37 const RegisterClassInfo &RegClassInfo; member in class:llvm::CriticalAntiDepBreaker
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| H A D | RegAllocBase.h | 66 RegisterClassInfo RegClassInfo; member in class:llvm::RegAllocBase
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| H A D | AggressiveAntiDepBreaker.h | 117 const RegisterClassInfo &RegClassInfo; member in class:llvm::AggressiveAntiDepBreaker
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| H A D | PostRASchedulerList.cpp | 82 RegisterClassInfo RegClassInfo; member in class:__anon13952::PostRAScheduler
291 RegClassInfo.runOnMachineFunction(Fn);
314 SchedulePostRATDList Scheduler(Fn, MLI, AA, RegClassInfo, AntiDepMode,
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| H A D | RegAllocGreedy.cpp | 663 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
767 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(VirtReg.reg)) <
768 RegClassInfo.getNumAllocatableRegs(MRI->getRegClass(Intf->reg)));
847 unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg);
878 unsigned MinCost = RegClassInfo.getMinCost(RC);
888 OrderLimit = RegClassInfo.getLastCostChange(RC);
901 << PrintReg(RegClassInfo.getLastCalleeSavedAlias(PhysReg), TRI)
1225 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1517 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1585 if (!RegClassInfo
[all...] |
| H A D | RegAllocBasic.cpp | 226 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo, Matrix);
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| H A D | CriticalAntiDepBreaker.cpp | 34 TRI(MF.getSubtarget().getRegisterInfo()), RegClassInfo(RCI),
383 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC);
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| H A D | RegAllocFast.cpp | 59 RegisterClassInfo RegClassInfo; member in class:__anon13959::RAFast
552 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
1092 RegClassInfo.runOnMachineFunction(Fn);
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| H A D | AllocationOrder.h | 41 const RegisterClassInfo &RegClassInfo);
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| H A D | AllocationOrder.cpp | 27 const RegisterClassInfo &RegClassInfo)
28 : Begin(0), End(0), Pos(0), RCI(RegClassInfo), OwnedBegin(false) {
25 AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, const RegisterClassInfo &RegClassInfo) argument
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| H A D | CriticalAntiDepBreaker.h | 40 const RegisterClassInfo &RegClassInfo; member in class:llvm::CriticalAntiDepBreaker
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| H A D | AggressiveAntiDepBreaker.h | 122 const RegisterClassInfo &RegClassInfo; member in class:llvm::AggressiveAntiDepBreaker
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| H A D | RegAllocBase.h | 95 RegisterClassInfo RegClassInfo;
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| H A D | RegAllocFast.cpp | 62 RegisterClassInfo RegClassInfo; member in class:__anon22644::RAFast
489 !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint)))
503 ArrayRef<unsigned> AO = RegClassInfo.getOrder(RC);
765 if (RegClassInfo.isAllocatable(*I))
896 if (!RegClassInfo.isAllocatable(Reg)) continue;
985 if (!RegClassInfo.isAllocatable(Reg)) continue;
1041 RegClassInfo.runOnMachineFunction(Fn);
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| H A D | RegisterCoalescer.cpp | 91 RegisterClassInfo RegClassInfo; member in class:__anon22654::RegisterCoalescer
1087 unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2;
1106 unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC);
1136 unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC);
1141 unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC);
1828 RegClassInfo.runOnMachineFunction(fn);
1861 RegClassInfo.isProperSubClass(MRI->getRegClass(SrcReg)))
1864 RegClassInfo.isProperSubClass(MRI->getRegClass(DstReg)))
1911 if (RegClassInfo.isProperSubClass(MRI->getRegClass(Reg)))
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| H A D | CriticalAntiDepBreaker.cpp | 35 RegClassInfo(RCI),
388 ArrayRef<unsigned> Order = RegClassInfo.getOrder(RC);
535 if (!RegClassInfo.isAllocatable(AntiDepReg))
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| H A D | PostRASchedulerList.cpp | 84 RegisterClassInfo RegClassInfo; member in class:__anon22640::PostRAScheduler
212 RegClassInfo.runOnMachineFunction(Fn);
239 SchedulePostRATDList Scheduler(Fn, MLI, MDT, AA, RegClassInfo, AntiDepMode,
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| H A D | RegAllocBasic.cpp | 236 RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
339 RegClassInfo.getOrder(MRI->getRegClass(VirtReg->reg)).front());
489 RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg));
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| H A D | AggressiveAntiDepBreaker.cpp | 124 RegClassInfo(RCI),
623 ArrayRef<unsigned> Order = RegClassInfo.getOrder(SuperRC);
642 if (!RegClassInfo.isAllocatable(NewSuperReg)) continue;
823 if (!RegClassInfo.isAllocatable(AntiDepReg)) {
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| H A D | RegAllocGreedy.cpp | 637 if (unsigned CSR = RegClassInfo.getLastCalleeSavedAlias(PhysReg))
957 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1222 bool SingleInstrs = RegClassInfo.isProperSubClass(MRI->getRegClass(Reg));
1557 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo);
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| /external/llvm/include/llvm/CodeGen/ |
| H A D | MachineScheduler.h | 108 RegisterClassInfo *RegClassInfo; member in struct:llvm::MachineSchedContext
356 RegisterClassInfo *RegClassInfo; member in class:llvm::ScheduleDAGMILive
397 RegClassInfo(C->RegClassInfo), DFSResult(nullptr),
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| /external/llvm/lib/Target/AMDGPU/ |
| H A D | SIMachineScheduler.h | 444 RPTracker.init(&MF, RegClassInfo, LIS, BB, RegionBegin, false, false);
|