/external/llvm/lib/Target/Mips/ |
H A D | MipsAnalyzeImmediate.cpp | 45 AddInstr(SeqLs, Inst(SLL, Shamt)); 80 // Replace a ADDiu & SLL pair with a LUi. 83 // SLL 18 87 // Check if the first two instructions are ADDiu and SLL and the shift amount 90 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) 133 SLL = Mips::SLL; 138 SLL = Mips::DSLL;
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H A D | MipsAnalyzeImmediate.h | 43 /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to 50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi. 58 unsigned ADDiu, ORi, SLL, LUi; member in class:llvm::MipsAnalyzeImmediate
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H A D | MipsFastISel.cpp | 1371 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8); 1399 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8); 1401 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24); 1589 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt); 1742 Opcode = Mips::SLL;
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H A D | MipsISelLowering.cpp | 1220 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm); 1312 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1317 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 1575 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1580 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3); 2321 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); local 2322 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
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/external/pcre/dist2/src/sljit/ |
H A D | sljitNativeSPARC_32.c | 59 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst))); 70 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst))); 92 FAIL_IF(push_inst(compiler, SLL | D(TMP_REG1) | S1(TMP_REG1) | IMM(1), DR(TMP_REG1))); 126 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
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H A D | sljitNativeMIPS_32.c | 90 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(24), DR(dst))); 108 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(16), DR(dst))); 147 FAIL_IF(push_inst(compiler, SLL | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS)); 192 FAIL_IF(push_inst(compiler, SLL | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1))); 195 return push_inst(compiler, SLL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG); 268 FAIL_IF(push_inst(compiler, SLL | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1))); 328 EMIT_SHIFT(SLL, SLLV);
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H A D | sljitNativeMIPS_64.c | 208 return push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(0), DR(dst)); 239 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL, SLL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS)); 284 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1))); 287 return push_inst(compiler, SELECT_OP(DSRL32, SLL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG); 360 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1))); 423 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV);
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H A D | sljitNativeSPARC_common.c | 154 #define SLL (OPC1(0x2) | OPC3(0x25)) macro 174 #define SLL_W SLL
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H A D | sljitNativeMIPS_common.c | 165 #define SLL (HI(0) | LO(0)) macro 189 #define SLL_W SLL
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/external/clang/test/CodeGen/ |
H A D | xcore-stringtype.c | 33 long long LL, unsigned long long ULL, signed long long SLL, 30 builtinType(_Bool B, char C, unsigned char UC, signed char SC, short S, unsigned short US, signed short SS, int I, unsigned int UI, signed int SI, long L, unsigned long UL, signed long SL, long long LL, unsigned long long ULL, signed long long SLL, float F, double D, long double LD) argument
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/external/v8/src/mips/ |
H A D | assembler-mips-inl.h | 438 Instr nop = SPECIAL | SLL; 451 Instr nop = SPECIAL | SLL;
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H A D | constants-mips.h | 411 SLL = ((0U << 3) + 0), 927 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) |
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H A D | assembler-mips.cc | 640 bool ret = (opcode == SPECIAL && function == SLL && 1722 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
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/external/v8/src/mips64/ |
H A D | assembler-mips64-inl.h | 420 Instr nop = SPECIAL | SLL; 433 Instr nop = SPECIAL | SLL;
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H A D | constants-mips64.h | 394 SLL = ((0U << 3) + 0), 963 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) |
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/external/valgrind/none/tests/mips64/ |
H A D | shift_instructions.c | 9 ROTR, ROTRV, SLL, SLLV, enumerator in enum:__anon29714 159 case SLL:
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsTargetStreamer.cpp | 215 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI); 219 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
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H A D | MipsMCCodeEmitter.cpp | 224 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0 227 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
H A D | MipsISelLowering.cpp | 1020 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1089 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1248 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1298 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
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/external/capstone/arch/SystemZ/ |
H A D | SystemZGenAsmWriter.inc | 843 9443767U, // SLL
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/external/v8/src/s390/ |
H A D | assembler-s390.cc | 1618 rs_form(SLL, r1, r0, opnd, 0); 1623 rs_form(SLL, r1, r0, r0, opnd.immediate());
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H A D | simulator-s390.h | 603 EVALUATE(SLL);
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/external/capstone/arch/Mips/ |
H A D | MipsGenAsmWriter.inc | 1459 1107318344U, // SLL 3173 0U, // SLL 5308 // (SLL ZERO, ZERO, 0)
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/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 3123 TOut.emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, STI); 3241 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI); 3488 FirstShift = Mips::SLL; 3493 SecondShift = Mips::SLL;
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/external/clang/lib/Sema/ |
H A D | SemaOverload.cpp | 7256 // (we could precompute SLL x UI for all known platforms, but it's 7261 Flt, Dbl, LDbl, SI, SL, SLL, S128, UI, UL, ULL, U128 7268 /* SI*/ { Flt, Dbl, LDbl, SI, SL, SLL, S128, UI, UL, ULL, U128 }, 7269 /* SL*/ { Flt, Dbl, LDbl, SL, SL, SLL, S128, Dep, UL, ULL, U128 }, 7270 /* SLL*/ { Flt, Dbl, LDbl, SLL, SLL, SLL, S128, Dep, Dep, ULL, U128 }, 7298 assert(L == SLL || R == SLL); [all...] |