Searched refs:SLL (Results 1 - 25 of 33) sorted by relevance

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/external/llvm/lib/Target/Mips/
H A DMipsAnalyzeImmediate.cpp45 AddInstr(SeqLs, Inst(SLL, Shamt));
80 // Replace a ADDiu & SLL pair with a LUi.
83 // SLL 18
87 // Check if the first two instructions are ADDiu and SLL and the shift amount
90 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16))
133 SLL = Mips::SLL;
138 SLL = Mips::DSLL;
H A DMipsAnalyzeImmediate.h43 /// GetInstSeqLsSLL - Get instruction sequences which end with a SLL to
50 /// ReplaceADDiuSLLWithLUi - Replace an ADDiu & SLL pair with a LUi.
58 unsigned ADDiu, ORi, SLL, LUi; member in class:llvm::MipsAnalyzeImmediate
H A DMipsFastISel.cpp1371 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1399 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1401 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1589 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1742 Opcode = Mips::SLL;
H A DMipsISelLowering.cpp1220 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1312 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1317 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1575 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1580 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
2321 SDValue SLL = DAG.getNode(ISD::SHL, DL, MVT::i64, LWR, Const32); local
2322 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i64, SLL, Const32);
/external/pcre/dist2/src/sljit/
H A DsljitNativeSPARC_32.c59 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(24), DR(dst)));
70 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src2) | IMM(16), DR(dst)));
92 FAIL_IF(push_inst(compiler, SLL | D(TMP_REG1) | S1(TMP_REG1) | IMM(1), DR(TMP_REG1)));
126 FAIL_IF(push_inst(compiler, SLL | D(dst) | S1(src1) | ARG2(flags, src2), DR(dst)));
H A DsljitNativeMIPS_32.c90 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(24), DR(dst)));
108 FAIL_IF(push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(16), DR(dst)));
147 FAIL_IF(push_inst(compiler, SLL | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS));
192 FAIL_IF(push_inst(compiler, SLL | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
195 return push_inst(compiler, SLL | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG);
268 FAIL_IF(push_inst(compiler, SLL | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
328 EMIT_SHIFT(SLL, SLLV);
H A DsljitNativeMIPS_64.c208 return push_inst(compiler, SLL | T(src2) | D(dst) | SH_IMM(0), DR(dst));
239 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL, SLL) | T(TMP_REG1) | D(TMP_REG1) | SH_IMM(1), UNMOVABLE_INS));
284 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
287 return push_inst(compiler, SELECT_OP(DSRL32, SLL) | TA(OVERFLOW_FLAG) | DA(OVERFLOW_FLAG) | SH_IMM(31), OVERFLOW_FLAG);
360 FAIL_IF(push_inst(compiler, SELECT_OP(DSLL32, SLL) | TA(ULESS_FLAG) | D(TMP_REG1) | SH_IMM(31), DR(TMP_REG1)));
423 EMIT_SHIFT(DSLL, DSLL32, SLL, DSLLV, SLLV);
H A DsljitNativeSPARC_common.c154 #define SLL (OPC1(0x2) | OPC3(0x25)) macro
174 #define SLL_W SLL
H A DsljitNativeMIPS_common.c165 #define SLL (HI(0) | LO(0)) macro
189 #define SLL_W SLL
/external/clang/test/CodeGen/
H A Dxcore-stringtype.c33 long long LL, unsigned long long ULL, signed long long SLL,
30 builtinType(_Bool B, char C, unsigned char UC, signed char SC, short S, unsigned short US, signed short SS, int I, unsigned int UI, signed int SI, long L, unsigned long UL, signed long SL, long long LL, unsigned long long ULL, signed long long SLL, float F, double D, long double LD) argument
/external/v8/src/mips/
H A Dassembler-mips-inl.h438 Instr nop = SPECIAL | SLL;
451 Instr nop = SPECIAL | SLL;
H A Dconstants-mips.h411 SLL = ((0U << 3) + 0),
927 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) |
H A Dassembler-mips.cc640 bool ret = (opcode == SPECIAL && function == SLL &&
1722 GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa & 0x1F, SLL);
/external/v8/src/mips64/
H A Dassembler-mips64-inl.h420 Instr nop = SPECIAL | SLL;
433 Instr nop = SPECIAL | SLL;
H A Dconstants-mips64.h394 SLL = ((0U << 3) + 0),
963 FunctionFieldToBitNumber(BREAK) | FunctionFieldToBitNumber(SLL) |
/external/valgrind/none/tests/mips64/
H A Dshift_instructions.c9 ROTR, ROTRV, SLL, SLLV, enumerator in enum:__anon29714
159 case SLL:
/external/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsTargetStreamer.cpp215 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
219 emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
H A DMipsMCCodeEmitter.cpp224 // Unfortunately in MIPS both NOP and SLL will come in with Binary == 0
227 if ((Opcode != Mips::NOP) && (Opcode != Mips::SLL) &&
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
H A DMipsISelLowering.cpp1020 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1089 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
1248 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1298 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes)
/external/capstone/arch/SystemZ/
H A DSystemZGenAsmWriter.inc843 9443767U, // SLL
/external/v8/src/s390/
H A Dassembler-s390.cc1618 rs_form(SLL, r1, r0, opnd, 0);
1623 rs_form(SLL, r1, r0, r0, opnd.immediate());
H A Dsimulator-s390.h603 EVALUATE(SLL);
/external/capstone/arch/Mips/
H A DMipsGenAsmWriter.inc1459 1107318344U, // SLL
3173 0U, // SLL
5308 // (SLL ZERO, ZERO, 0)
/external/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp3123 TOut.emitRRI(Mips::SLL, ZeroReg, ZeroReg, 0, IDLoc, STI);
3241 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
3488 FirstShift = Mips::SLL;
3493 SecondShift = Mips::SLL;
/external/clang/lib/Sema/
H A DSemaOverload.cpp7256 // (we could precompute SLL x UI for all known platforms, but it's
7261 Flt, Dbl, LDbl, SI, SL, SLL, S128, UI, UL, ULL, U128
7268 /* SI*/ { Flt, Dbl, LDbl, SI, SL, SLL, S128, UI, UL, ULL, U128 },
7269 /* SL*/ { Flt, Dbl, LDbl, SL, SL, SLL, S128, Dep, UL, ULL, U128 },
7270 /* SLL*/ { Flt, Dbl, LDbl, SLL, SLL, SLL, S128, Dep, Dep, ULL, U128 },
7298 assert(L == SLL || R == SLL);
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