Searched refs:SRW (Results 1 - 10 of 10) sorted by relevance
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| H A D | MSP430RegisterInfo.cpp | 88 Reserved.set(MSP430::SRW);
138 // The SRW implicit def is dead.
153 // The SRW implicit def is dead.
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| H A D | MSP430ISelLowering.cpp | 799 // Res = SRW & 1, no processing is required
802 // Res = ~(SRW & 1)
807 // C = ~Z, thus Res = SRW & 1, no processing is required
809 // Res = ~((SRW >> 1) & 1)
816 // C = ~Z for AND instruction, thus we can put Res = ~(SRW & 1), however,
817 // Res = (SRW >> 1) & 1 is 1 word shorter.
823 SDValue SR = DAG.getCopyFromReg(DAG.getEntryNode(), dl, MSP430::SRW,
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| /external/pcre/dist2/src/sljit/ |
| H A D | sljitNativePPC_32.c | 228 return push_inst(compiler, SRW | RC(flags) | S(src1) | A(dst) | B(src2));
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| H A D | sljitNativePPC_64.c | 367 return push_inst(compiler, ((flags & ALT_FORM2) ? SRW : SRD) | RC(flags) | S(src1) | A(dst) | B(src2));
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| H A D | sljitNativePPC_common.c | 210 #define SRW (HI(31) | LO(536)) macro
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 1583 MIOpC == PPC::SRW || MIOpC == PPC::SRWo ||
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| H A D | PPCISelDAGToDAG.cpp | 3967 // SLW and SRW always clear the higher-order bits.
3969 Op32.getMachineOpcode() == PPC::SRW) {
4182 case PPC::SRW: NewOpcode = PPC::SRW8; break;
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| H A D | PPCISelLowering.cpp | 8629 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
9372 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 4838 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
5188 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
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| /external/capstone/arch/PowerPC/ |
| H A D | PPCGenAsmWriter.inc | 853 23321U, // SRW
2126 0U, // SRW
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