/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonMachineScheduler.cpp | 38 /// Check if scheduling of this SU is possible 43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { argument 44 if (!SU || !SU->getInstr()) 49 switch (SU->getInstr()->getOpcode()) { 51 if (!ResourcesModel->canReserveResources(*SU->getInstr())) 75 if (I->getSUnit() == SU) 83 bool VLIWResourceModel::reserveResources(SUnit *SU) { argument 86 if (!SU) { 92 // If this SU doe 184 SUnit *SU = SchedImpl->pickNode(IsTopNode); local 228 releaseTopNode(SUnit *SU) argument 245 releaseBottomNode(SUnit *SU) argument 277 checkHazard(SUnit *SU) argument 288 releaseNode(SUnit *SU, unsigned ReadyCycle) argument 329 bumpNode(SUnit *SU) argument 367 SUnit *SU = *(Pending.begin()+i); local 387 removeReady(SUnit *SU) argument 416 traceCandidate(const char *Label, const ReadyQueue &Q, SUnit *SU, PressureChange P) argument 431 getSingleUnscheduledPred(SUnit *SU) argument 449 getSingleUnscheduledSucc(SUnit *SU) argument 474 SchedulingCost(ReadyQueue &Q, SUnit *SU, SchedCandidate &Candidate, RegPressureDelta &Delta, bool verbose) argument 649 SUnit *SU; local 691 schedNode(SUnit *SU, bool IsTopNode) argument [all...] |
H A D | HexagonMachineScheduler.h | 86 bool isResourceAvailable(SUnit *SU); 87 bool reserveResources(SUnit *SU); 114 SUnit *SU; member in struct:llvm::ConvergingVLIWScheduler::SchedCandidate 122 SchedCandidate(): SU(nullptr), SCost(0) {} 175 bool checkHazard(SUnit *SU); 177 void releaseNode(SUnit *SU, unsigned ReadyCycle); 181 void bumpNode(SUnit *SU); 185 void removeReady(SUnit *SU); 213 void schedNode(SUnit *SU, bool IsTopNode) override; 215 void releaseTopNode(SUnit *SU) overrid [all...] |
/external/llvm/lib/CodeGen/ |
H A D | LatencyPriorityQueue.cpp | 55 /// of SU, return it, otherwise return null. 56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument 58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 73 void LatencyPriorityQueue::push(SUnit *SU) { argument 77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 79 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; 84 Queue.push_back(SU); 92 scheduledNode(SUnit *SU) argument 105 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument 134 remove(SUnit *SU) argument [all...] |
H A D | ScheduleDAGInstrs.cpp | 81 dbgs() << "SU(" << su->NodeNum << ")"; 243 /// the exit SU to the register defs and use list. This is because we want to 281 /// MO is an operand of SU's instruction that defines a physical register. Add 282 /// data dependencies from SU to any uses of the physical register. 283 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { argument 284 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); 295 SUnit *UseSU = I->SU; 296 if (UseSU == SU) 305 Dep = SDep(SU, SDep::Artificial); 309 SU 326 addPhysRegDeps(SUnit *SU, unsigned OperIdx) argument 421 addVRegDefDeps(SUnit *SU, unsigned OperIdx) argument 530 addVRegUseDeps(SUnit *SU, unsigned OperIdx) argument 652 SUnit *SU = newSUnit(&MI); local 689 collectVRegUses(SUnit *SU) argument 745 insert(SUnit *SU, ValueType V) argument 783 addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap) argument 790 addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap, ValueType V) argument 925 SUnit *SU = MISUnitMap[&MI]; local 1439 visitPreorder(const SUnit *SU) argument 1447 visitPostorderNode(const SUnit *SU) argument 1599 follow(const SUnit *SU) argument 1619 hasDataSucc(const SUnit *SU) argument 1637 const SUnit *SU = &*SI; local [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | ResourcePriorityQueue.cpp | 70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { argument 72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, argument 110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 145 static unsigned numberCtrlDepsInSU(SUnit *SU) { argument 147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 155 static unsigned numberCtrlPredInSU(SUnit *SU) { argument 173 SUnit *SU = &(*SUnits)[i]; local 215 getSingleUnscheduledPred(SUnit *SU) argument 231 push(SUnit *SU) argument 246 isResourceAvailable(SUnit *SU) argument 289 reserveResources(SUnit *SU) argument 326 rawRegPressureDelta(SUnit *SU, unsigned RCId) argument 360 regPressureDelta(SUnit *SU, bool RawPressure) argument 401 SUSchedulingCost(SUnit *SU) argument 471 scheduledNode(SUnit *SU) argument 547 initNumRegDefsLeft(SUnit *SU) argument 579 adjustPriorityOfUnscheduledPreds(SUnit *SU) argument 632 remove(SUnit *SU) argument [all...] |
H A D | ScheduleDAGRRList.cpp | 185 /// IsReachable - Checks if SU is reachable from TargetSU. 186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument 187 return Topo.IsReachable(SU, TargetSU); 190 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument 193 return Topo.WillCreateCycle(SU, TargetSU); 196 /// AddPred - adds a predecessor edge to SUnit SU. 199 void AddPred(SUnit *SU, const SDep &D) { argument 200 Topo.AddPred(SU, D.getSUnit()); 201 SU 207 RemovePred(SUnit *SU, const SDep &D) argument 213 isReady(SUnit *SU) argument 365 ReleasePred(SUnit *SU, const SDep *PredEdge) argument 525 ReleasePredecessors(SUnit *SU) argument 622 AdvancePastStalls(SUnit *SU) argument 664 EmitNode(SUnit *SU) argument 706 ScheduleNodeBottomUp(SUnit *SU) argument 805 UnscheduleNodeBottomUp(SUnit *SU) argument 903 SUnit *SU = *I; local 913 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument 935 isOperandOf(const SUnit *SU, SDNode *N) argument 946 CopyAndMoveSuccessors(SUnit *SU) argument 1135 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVectorImpl<SUnit*> &Copies) argument 1210 CheckForLiveRegDef(SUnit *SU, unsigned Reg, SUnit **LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs, const TargetRegisterInfo *TRI) argument 1232 CheckForLiveRegDefMasked(SUnit *SU, const uint32_t *RegMask, ArrayRef<SUnit*> LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVectorImpl<unsigned> &LRegs) argument 1259 DelayForLiveRegsBottomUp(SUnit *SU, SmallVectorImpl<unsigned> &LRegs) argument 1338 SUnit *SU = Interferences[i-1]; local 1508 SUnit *SU = PickNodeToScheduleBottomUp(); local 1797 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); variable [all...] |
H A D | ScheduleDAGVLIW.cpp | 87 void releaseSucc(SUnit *SU, const SDep &D); 88 void releaseSuccessors(SUnit *SU); 89 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle); 116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { argument 131 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); 140 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { argument 142 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 147 releaseSucc(SU, *I); 154 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigne argument [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCHazardRecognizers.h | 31 bool isLoadAfterStore(SUnit *SU); 32 bool isBCTRAfterSet(SUnit *SU); 40 HazardType getHazardType(SUnit *SU, int Stalls) override; 41 bool ShouldPreferAnother(SUnit* SU) override; 42 unsigned PreEmitNoops(SUnit *SU) override; 43 void EmitInstruction(SUnit *SU) override; 79 HazardType getHazardType(SUnit *SU, int Stalls) override; 80 void EmitInstruction(SUnit *SU) override;
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H A D | PPCHazardRecognizers.cpp | 26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { argument 28 if (isBCTRAfterSet(SU)) 31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); 38 // SU is a load; for any predecessors in this dispatch group, that are stores, 40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) { 41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); 45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier()) 49 if (SU->Preds[i].getSUnit() == CurGroup[j]) 56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { argument 141 getHazardType(SUnit *SU, int Stalls) argument 148 ShouldPreferAnother(SUnit *SU) argument 157 PreEmitNoops(SUnit *SU) argument 176 EmitInstruction(SUnit *SU) argument 328 getHazardType(SUnit *SU, int Stalls) argument 388 EmitInstruction(SUnit *SU) argument [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
H A D | SPUHazardRecognizers.h | 33 virtual HazardType getHazardType(SUnit *SU, int Stalls); 34 virtual void EmitInstruction(SUnit *SU);
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/external/llvm/include/llvm/CodeGen/ |
H A D | ResourcePriorityQueue.h | 84 void addNode(const SUnit *SU) override { 88 void updateNode(const SUnit *SU) override {} 104 /// Single cost function reflecting benefit of scheduling SU 106 int SUSchedulingCost (SUnit *SU); 110 void initNumRegDefsLeft(SUnit *SU); 111 void updateNumRegDefsLeft(SUnit *SU); 112 int regPressureDelta(SUnit *SU, bool RawPressure = false); 113 int rawRegPressureDelta (SUnit *SU, unsigned RCId); 121 void remove(SUnit *SU) override; 125 bool isResourceAvailable(SUnit *SU); [all...] |
H A D | ScheduleDAGInstrs.h | 38 SUnit *SU; member in struct:llvm::VReg2SUnit 40 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) argument 41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} 53 unsigned OperandIndex, SUnit *SU) 54 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} 60 SUnit *SU; member in struct:llvm::PhysRegSUOper 64 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} 166 /// No other SU ever gets scheduled around it (except in the special 193 /// Add dependencies as needed from all SUs in list to SU 52 VReg2SUnitOperIdx(unsigned VReg, LaneBitmask LaneMask, unsigned OperandIndex, SUnit *SU) argument 194 addChainDependencies(SUnit *SU, SUList &sus, unsigned Latency) argument [all...] |
H A D | LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) override { 61 void updateNode(const SUnit *SU) override { 84 void remove(SUnit *SU) override; 93 void AdjustPriorityOfUnscheduledPreds(SUnit *SU); 94 SUnit *getSingleUnscheduledPred(SUnit *SU);
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H A D | MachineScheduler.h | 212 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0; 216 virtual void releaseTopNode(SUnit *SU) = 0; 219 virtual void releaseBottomNode(SUnit *SU) = 0; 288 /// \brief Add a DAG edge to the given SU with the given predecessor 332 void updateQueues(SUnit *SU, bool IsTopNode); 346 void releaseSucc(SUnit *SU, SDep *SuccEdge); 347 void releaseSuccessors(SUnit *SU); 348 void releasePred(SUnit *SU, SDep *PredEdge); 349 void releasePredecessors(SUnit *SU); 365 // Map each SU t 425 getPressureDiff(const SUnit *SU) argument 521 find(SUnit *SU) argument 525 push(SUnit *SU) argument 816 SUnit *SU; member in struct:llvm::GenericSchedulerBase::SchedCandidate [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
H A D | ScheduleDAGRRList.cpp | 189 /// IsReachable - Checks if SU is reachable from TargetSU. 190 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { argument 191 return Topo.IsReachable(SU, TargetSU); 194 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will 196 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { argument 197 return Topo.WillCreateCycle(SU, TargetSU); 200 /// AddPred - adds a predecessor edge to SUnit SU. 203 void AddPred(SUnit *SU, const SDep &D) { argument 204 Topo.AddPred(SU, D.getSUnit()); 205 SU 211 RemovePred(SUnit *SU, const SDep &D) argument 217 isReady(SUnit *SU) argument 366 ReleasePred(SUnit *SU, const SDep *PredEdge) argument 423 ReleasePredecessors(SUnit *SU) argument 503 AdvancePastStalls(SUnit *SU) argument 545 EmitNode(SUnit *SU) argument 589 ScheduleNodeBottomUp(SUnit *SU) argument 672 UnscheduleNodeBottomUp(SUnit *SU) argument 733 SUnit *SU = *I; local 743 BacktrackBottomUp(SUnit *SU, SUnit *BtSU) argument 768 isOperandOf(const SUnit *SU, SDNode *N) argument 779 CopyAndMoveSuccessors(SUnit *SU) argument 971 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVector<SUnit*, 2> &Copies) argument 1040 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs, const TargetRegisterInfo *TRI) argument 1065 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) argument 1286 SUnit *SU = PickNodeToScheduleBottomUp(); local 1334 ReleaseSuccessors(SUnit *SU) argument 1348 ScheduleNodeTopDown(SUnit *SU) argument 1407 isReady(SUnit* SU, unsigned CurCycle) const argument 1592 remove(SUnit *SU) argument 1682 SUnit *SU = popFromQueue(DumpQueue, DumpPicker, scheduleDAG); local 1729 CalcNodeSethiUllmanNumber(const SUnit *SU, std::vector<unsigned> &SUNumbers) argument 1764 addNode(const SUnit *SU) argument 1771 updateNode(const SUnit *SU) argument 1882 RegPressureDiff(SUnit *SU, unsigned &LiveUses) const argument 1922 ScheduledNode(SUnit *SU) argument 1991 UnscheduledNode(SUnit *SU) argument 2078 closestSucc(const SUnit *SU) argument 2097 calcMaxScratches(const SUnit *SU) argument 2109 hasOnlyLiveInOpers(const SUnit *SU) argument 2132 hasOnlyLiveOutUses(const SUnit *SU) argument 2161 initVRegCycle(SUnit *SU) argument 2181 resetVRegCycle(SUnit *SU) argument 2199 hasVRegCycleUse(const SUnit *SU) argument 2219 BUHasStall(SUnit *SU, int Height, RegReductionPQBase *SPQ) argument 2434 isReady(SUnit *SU, unsigned CurCycle) const argument 2483 isReady(SUnit *SU, unsigned CurCycle) const argument 2493 canEnableCoalescing(SUnit *SU) argument 2606 canClobber(const SUnit *SU, const SUnit *Op) argument 2627 canClobberReachingPhysRegUse(const SUnit *DepSU, const SUnit *SU, ScheduleDAGRRList *scheduleDAG, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) argument 2659 canClobberPhysRegDefs(const SUnit *SuccSU, const SUnit *SU, const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) argument 2725 SUnit *SU = &(*SUnits)[i]; local 2816 SUnit *SU = &(*SUnits)[i]; local 2893 LimitedSumOfUnscheduledPredsOfSuccs(const SUnit *SU, unsigned Limit) argument [all...] |
H A D | ScheduleDAGList.cpp | 81 void ReleaseSucc(SUnit *SU, const SDep &D); 82 void ReleaseSuccessors(SUnit *SU); 83 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle); 108 void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) { argument 121 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); 129 void ScheduleDAGList::ReleaseSuccessors(SUnit *SU) { argument 131 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 136 ReleaseSucc(SU, *I); 143 void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigne argument [all...] |
H A D | ScheduleDAGFast.cpp | 80 /// AddPred - adds a predecessor edge to SUnit SU. 82 void AddPred(SUnit *SU, const SDep &D) { argument 83 SU->addPred(D); 86 /// RemovePred - removes a predecessor edge from SUnit SU. 88 void RemovePred(SUnit *SU, const SDep &D) { argument 89 SU->removePred(D); 93 void ReleasePred(SUnit *SU, SDep *PredEdge); 94 void ReleasePredecessors(SUnit *SU, unsigned CurCycle); 134 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { argument 155 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigne argument 177 ScheduleNodeBottomUp(SUnit *SU, unsigned CurCycle) argument 207 CopyAndMoveSuccessors(SUnit *SU) argument 380 InsertCopiesAndMoveSuccs(SUnit *SU, unsigned Reg, const TargetRegisterClass *DestRC, const TargetRegisterClass *SrcRC, SmallVector<SUnit*, 2> &Copies) argument 438 CheckForLiveRegDef(SUnit *SU, unsigned Reg, std::vector<SUnit*> &LiveRegDefs, SmallSet<unsigned, 4> &RegAdded, SmallVector<unsigned, 4> &LRegs, const TargetRegisterInfo *TRI) argument 464 DelayForLiveRegsBottomUp(SUnit *SU, SmallVector<unsigned, 4> &LRegs) argument [all...] |
H A D | ScheduleDAGSDNodes.h | 87 void InitVRegCycleFlag(SUnit *SU); 91 void InitNumRegDefsLeft(SUnit *SU); 95 virtual void ComputeLatency(SUnit *SU); 113 virtual void dumpNode(const SUnit *SU) const; 115 virtual std::string getGraphNodeLabel(const SUnit *SU) const; 129 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
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/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
H A D | ScheduleDAGEmit.cpp | 35 void ScheduleDAG::EmitPhysRegCopy(SUnit *SU, argument 37 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 46 for (SUnit::const_succ_iterator II = SU->Succs.begin(), 47 EE = SU->Succs.end(); II != EE; ++II) { 59 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC); 60 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
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H A D | LatencyPriorityQueue.cpp | 54 /// of SU, return it, otherwise return null. 55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { argument 57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 72 void LatencyPriorityQueue::push(SUnit *SU) { argument 76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 78 if (getSingleUnscheduledPred(I->getSUnit()) == SU) 81 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; 83 Queue.push_back(SU); 91 ScheduledNode(SUnit *SU) argument 104 AdjustPriorityOfUnscheduledPreds(SUnit *SU) argument 133 remove(SUnit *SU) argument [all...] |
/external/llvm/lib/Target/AMDGPU/ |
H A D | R600MachineScheduler.cpp | 58 SUnit *SU = nullptr; local 98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || 101 SU = pickAlu(); 102 if (!SU && !PhysicalRegCopy.empty()) { 103 SU = PhysicalRegCopy.front(); 106 if (SU) { 113 if (!SU) { 115 SU = pickOther(IDFetch); 116 if (SU) 121 if (!SU) { 144 schedNode(SUnit *SU, bool IsTopNode) argument 192 releaseTopNode(SUnit *SU) argument 196 releaseBottomNode(SUnit *SU) argument 295 getInstKind(SUnit* SU) argument 324 SUnit *SU = *It; local 433 SUnit *SU = AttemptFillSlot(3, true); local 442 SUnit *SU = AttemptFillSlot(Chan, false); local 456 SUnit *SU = nullptr; local [all...] |
H A D | SIMachineScheduler.cpp | 178 void SIScheduleBlock::addUnit(SUnit *SU) { argument 179 NodeNum2Index[SU->NodeNum] = SUnits.size(); 180 SUnits.push_back(SU); 187 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); 237 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { 245 for (SUnit* SU : TopReadySUs) { 250 TryCand.SU = SU; 279 SUnit *SU = TopReadySUs[0]; local 397 SUnit *SU = pickNode(); local 433 undoReleaseSucc(SUnit *SU, SDep *SuccEdge) argument 443 releaseSucc(SUnit *SU, SDep *SuccEdge) argument 463 releaseSuccessors(SUnit *SU, bool InOrOutBlock) argument 476 nodeScheduled(SUnit *SU) argument 623 isSUInBlock(SUnit *SU, unsigned ID) argument 633 SUnit *SU = &DAG->SUnits[i]; local 649 SUnit *SU = &DAG->SUnits[i]; local 665 SUnit *SU = &DAG->SUnits[i]; local 711 SUnit *SU = &DAG->SUnits[SUNum]; local 753 SUnit *SU = &DAG->SUnits[SUNum]; local 799 SUnit *SU = &DAG->SUnits[i]; local 825 SUnit *SU = &DAG->SUnits[SUNum]; local 866 SUnit *SU = &DAG->SUnits[i]; local 892 SUnit *SU = &DAG->SUnits[SUNum]; local 918 SUnit *SU = &DAG->SUnits[SUNum]; local 939 SUnit *SU = &DAG->SUnits[SUNum]; local 961 SUnit *SU = &DAG->SUnits[SUNum]; local 972 SUnit *SU = &DAG->SUnits[SUNum]; local 1005 SUnit *SU = &DAG->SUnits[SUNum]; local 1055 SUnit *SU = &DAG->SUnits[i]; local 1070 SUnit *SU = &DAG->SUnits[i]; local 1691 SUnit *SU = &SUnits[ScheduledSUnits[i]]; local 1814 SUnit *SU = &SUnits[i]; local 1885 SUnit *SU = &SUnits[*I]; local [all...] |
H A D | GCNHazardRecognizer.h | 50 void EmitInstruction(SUnit *SU) override; 52 HazardType getHazardType(SUnit *SU, int Stalls) override; 54 unsigned PreEmitNoops(SUnit *SU) override;
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/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) { argument 61 void updateNode(const SUnit *SU) { argument 84 virtual void remove(SUnit *SU); 95 void AdjustPriorityOfUnscheduledPreds(SUnit *SU); 96 SUnit *getSingleUnscheduledPred(SUnit *SU);
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/external/llvm/lib/Target/ARM/ |
H A D | ARMHazardRecognizer.cpp | 35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { argument 38 MachineInstr *MI = SU->getInstr(); 73 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls); 82 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) { argument 83 MachineInstr *MI = SU->getInstr(); 89 ScoreboardHazardRecognizer::EmitInstruction(SU);
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