Searched refs:getSchedClass (Results 1 - 25 of 30) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/
H A DTargetInstrInfo.cpp54 unsigned Class = MI->getDesc().getSchedClass();
71 unsigned DefClass = DefMI->getDesc().getSchedClass();
72 unsigned UseClass = UseMI->getDesc().getSchedClass();
86 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
89 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
99 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
110 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
119 unsigned DefClass = DefMI->getDesc().getSchedClass();
/external/llvm/lib/CodeGen/
H A DTargetSchedule.cpp79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass());
105 unsigned SchedClass = MI->getDesc().getSchedClass();
168 unsigned DefClass = DefMI->getDesc().getSchedClass();
241 unsigned SCIdx = TII->get(Opcode).getSchedClass();
H A DScoreboardHazardRecognizer.cpp125 unsigned idx = MCID->getSchedClass();
185 unsigned idx = MCID->getSchedClass();
H A DDFAPacketizer.cpp120 unsigned InsnClass = MID->getSchedClass();
131 unsigned InsnClass = MID->getSchedClass();
H A DTargetInstrInfo.cpp990 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
993 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
1005 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
1017 unsigned Class = MI.getDesc().getSchedClass();
1051 return ItinData->getStageLatency(MI.getDesc().getSchedClass());
1061 unsigned DefClass = DefMI.getDesc().getSchedClass();
1073 unsigned DefClass = DefMI.getDesc().getSchedClass();
1074 unsigned UseClass = UseMI.getDesc().getSchedClass();
1108 unsigned DefClass = DefMI.getDesc().getSchedClass();
H A DMachineCombiner.cpp296 unsigned Idx = TII->get(Opc).getSchedClass();
H A DMachineScheduler.cpp1793 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I);
1874 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2077 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
2306 const MCSchedClassDesc *SC = DAG->getSchedClass(SU);
/external/swiftshader/third_party/LLVM/lib/CodeGen/
H A DScoreboardHazardRecognizer.cpp123 unsigned idx = MCID->getSchedClass();
185 unsigned idx = MCID->getSchedClass();
H A DScheduleDAGInstrs.cpp633 unsigned DefClass = DefMI->getDesc().getSchedClass();
/external/llvm/lib/Target/AArch64/
H A DAArch64StorePairSuppress.cpp81 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass();
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
H A DSPUNopFiller.cpp139 int sc = instr.getDesc().getSchedClass();
/external/swiftshader/third_party/LLVM/include/llvm/MC/
H A DMCInstrDesc.h264 /// getSchedClass - Return the scheduling class for this instruction. The
269 unsigned getSchedClass() const { function in class:llvm::MCInstrDesc
/external/llvm/lib/MC/MCDisassembler/
H A DDisassembler.cpp167 unsigned SCClass = Desc.getSchedClass();
194 unsigned SCClass = Desc.getSchedClass();
/external/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
92 unsigned IIC = MCID->getSchedClass();
/external/llvm/utils/TableGen/
H A DCodeGenSchedule.h349 CodeGenSchedClass &getSchedClass(unsigned Idx) {
353 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
H A DSubtargetEmitter.cpp578 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
1120 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel"
1128 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
1291 const CodeGenSchedClass &SC = SchedModels.getSchedClass(VC);
1321 << SchedModels.getSchedClass(T.ToClassIdx).Name << '\n';
H A DCodeGenSchedule.cpp540 CodeGenSchedClass &SC = getSchedClass(SCIdx);
1329 SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans);
1568 const CodeGenSchedClass &SC = getSchedClass(SCIdx);
/external/llvm/include/llvm/CodeGen/
H A DScheduleDAGInstrs.h246 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { function in class:llvm::ScheduleDAGInstrs
/external/llvm/include/llvm/MC/
H A DMCInstrDesc.h528 unsigned getSchedClass() const { return SchedClass; } function in class:llvm::MCInstrDesc
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp2041 unsigned SchedClass = MI->getDesc().getSchedClass();
2251 unsigned SchedClass = MI->getDesc().getSchedClass();
2279 return MI->getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
2548 unsigned SchedClass = MI->getDesc().getSchedClass();
2567 unsigned SchedClass = MI->getDesc().getSchedClass();
2584 unsigned SchedClass = MI->getDesc().getSchedClass();
2608 unsigned SchedClass = MI->getDesc().getSchedClass();
4008 unsigned Latency = ItinData->getStageLatency(MI->getDesc().getSchedClass());
4183 const InstrStage &IS = *II.beginStage(MI->getDesc().getSchedClass());
4260 " Class: " << NewMI->getDesc().getSchedClass());
[all...]
H A DHexagonVLIWPacketizer.cpp938 auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass());
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.cpp380 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
728 unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass();
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp1982 unsigned Class = Desc.getSchedClass();
2232 unsigned DefClass = DefMCID.getSchedClass();
2233 unsigned UseClass = UseMCID.getSchedClass();
2512 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
2680 unsigned Class = MCID.getSchedClass();
2702 return ItinData->getStageLatency(get(Opcode).getSchedClass());
2737 unsigned DefClass = DefMI->getDesc().getSchedClass();
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp2778 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3076 unsigned Class = Desc.getSchedClass();
3334 unsigned DefClass = DefMCID.getSchedClass();
3335 unsigned UseClass = UseMCID.getSchedClass();
3785 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4034 unsigned Class = MCID.getSchedClass();
4064 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4101 unsigned DefClass = DefMI.getDesc().getSchedClass();
/external/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp176 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU);
184 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU);

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