Searched refs:reg4 (Results 1 - 25 of 42) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
H A Didct32x32_msa.c44 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
48 LD_SH8(tmp_buf, 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
58 DOTP_CONST_PAIR(reg0, reg4, cospi_16_64, cospi_16_64, reg0, reg4);
60 BUTTERFLY_4(reg4, reg0, reg2, reg6, vec1, vec3, vec2, vec0);
65 LD_SH8((tmp_buf + 16), 32, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
67 DOTP_CONST_PAIR(reg4, reg3, cospi_14_64, cospi_18_64, reg4, reg3);
71 vec0 = reg0 + reg4;
72 reg0 = reg0 - reg4;
128 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
354 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
434 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
[all...]
H A Didct16x16_msa.c15 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local
19 LD_SH8(input, 16, reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7);
23 TRANSPOSE8x8_SH_SH(reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg0, reg1,
24 reg2, reg3, reg4, reg5, reg6, reg7);
32 DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12);
33 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14);
34 SUB4(reg2, loc1, reg14, loc0, reg6, loc3, reg10, loc2, reg0, reg12, reg4,
75 loc1 = reg4 + loc0;
76 loc2 = reg4
109 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; local
[all...]
/external/elfutils/tests/
H A Drun-varlocs.sh59 [400500,400504) {reg4}
67 [400510,40051c) {reg4}
69 [40052a,400531) {GNU_entry_value(1) {reg4}, stack_value}
82 [400400,400403) {reg4}
83 [400403,40040b) {GNU_entry_value(1) {reg4}, stack_value}
110 [400400,400408) {reg4}
111 [400408,400423) {GNU_entry_value(1) {reg4}, stack_value}
H A Drun-readelf-zdebug-rel.sh87 [ 0] reg4
H A Drun-addrcfi.sh37 integer reg4 (%esp): location expression: call_frame_cfa stack_value
84 integer reg4 (%esp): location expression: call_frame_cfa stack_value
136 integer reg4 (%rsi): undefined
202 integer reg4 (%rsi): undefined
306 integer reg4 (r4): undefined
1328 integer reg4 (r4): undefined
2356 integer reg4 (r4): undefined
3382 integer reg4 (%r4): undefined
3459 integer reg4 (%r4): undefined
3537 integer reg4 (r
[all...]
/external/v8/src/interpreter/
H A Dbytecode-register.cc108 Register reg4, Register reg5) {
115 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) {
118 if (reg5.is_valid() && reg4.index() + 1 != reg5.index()) {
107 AreContiguous(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5) argument
H A Dbytecode-register.h67 Register reg4 = Register(),
/external/libyuv/files/source/
H A Drotate_msa.cc85 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
109 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7);
110 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3);
131 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7);
132 res8 = (v16u8)__msa_ilvr_w((v4i32)reg4, (v4i32)reg0);
133 res9 = (v16u8)__msa_ilvl_w((v4i32)reg4, (v4i32)reg0);
166 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
190 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg5, reg6, reg7);
191 ILVRL_W(reg0, reg4, reg1, reg5, res0, res1, res2, res3);
212 ILVRL_H(vec0, vec2, vec1, vec3, reg4, reg
[all...]
H A Drow_msa.cc774 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
794 reg4 = (v8u16)__msa_ilvod_b(zero, (v16i8)vec0);
800 reg4 *= const_0x42;
804 reg0 += reg4;
826 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
862 reg4 = __msa_hadd_u_h(vec0, vec0);
890 reg4 += __msa_hadd_u_h(vec0, vec0);
896 reg4 = (v8u16)__msa_srai_h((v8i16)reg4, 2);
904 reg8 += reg4 * const_0x2
1237 v4u32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
1506 v16u8 reg0, reg1, reg2, reg3, reg4, reg5, reg6; local
1553 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1648 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
1705 v8u16 reg0, reg1, reg2, reg3, reg4, reg5; local
2666 v4i32 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9; local
[all...]
H A Dscale_msa.cc133 v8u16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; local
161 reg4 = (v8u16)__msa_pckev_d((v2i64)reg2, (v2i64)reg0);
165 reg4 += reg6;
167 reg4 = (v8u16)__msa_srari_h((v8i16)reg4, 2);
169 dst0 = (v16u8)__msa_pckev_b((v16i8)reg5, (v16i8)reg4);
/external/syslinux/core/
H A Dregdump.inc53 .reg4:
62 loop .reg4
/external/vixl/src/aarch64/
H A Doperands-aarch64.h477 const CPURegister& reg4 = NoReg,
491 const CPURegister& reg4 = NoCPUReg,
504 const VRegister& reg4 = NoVReg);
514 const VRegister& reg4 = NoVReg);
523 CPURegister reg4 = NoCPUReg)
524 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()),
527 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
H A Dmacro-assembler-aarch64.cc2789 const Register& reg4) {
2792 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2803 const FPRegister& reg4) {
2805 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2823 const Register& reg4) {
2825 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2833 const FPRegister& reg4) {
2835 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit();
2843 const CPURegister& reg4) {
2847 const CPURegister regs[] = {reg1, reg2, reg3, reg4};
2786 Include(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) argument
2800 Include(const FPRegister& reg1, const FPRegister& reg2, const FPRegister& reg3, const FPRegister& reg4) argument
2820 Exclude(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) argument
2830 Exclude(const FPRegister& reg1, const FPRegister& reg2, const FPRegister& reg3, const FPRegister& reg4) argument
2840 Exclude(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4) argument
[all...]
H A Dassembler-aarch64.cc4751 const CPURegister& reg4,
4762 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
4790 const CPURegister& reg4,
4799 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
4811 const VRegister& reg4) {
4816 match &= !reg4.IsValid() || reg4.IsSameFormat(reg1);
4824 const VRegister& reg4) {
4839 if (!reg4
[all...]
H A Dmacro-assembler-aarch64.h3364 const Register& reg4 = NoReg);
3368 const VRegister& reg4 = NoVReg);
3378 const Register& reg4 = NoReg);
3382 const VRegister& reg4 = NoVReg);
3386 const CPURegister& reg4 = NoCPUReg);
/external/vixl/src/aarch32/
H A Dmacro-assembler-aarch32.cc450 CPURegister reg4) {
458 PushRegister(reg4);
466 uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) |
471 int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() +
495 if (reg4.GetType() == CPURegister::kRRegister) {
496 available_registers.Remove(Register(reg4.GetCode()));
506 PushRegister(reg4);
519 PreparePrintfArgument(reg4, &core_count, &vfp_count, &printf_type);
523 // One 32 bit argument (reg4) has been left on the stack => align the
593 // If register reg4 wa
446 Printf(const char* format, CPURegister reg1, CPURegister reg2, CPURegister reg3, CPURegister reg4) argument
[all...]
H A Dinstructions-aarch32.h468 RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
470 RegisterToList(reg3) | RegisterToList(reg4)) {}
557 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4)
559 RegisterToList(reg3) | RegisterToList(reg4)) {}
/external/v8/src/arm64/
H A Dassembler-arm64.h350 Register reg4 = NoReg);
358 const CPURegister& reg4 = NoReg,
371 const CPURegister& reg4 = NoCPUReg,
390 CPURegister reg4 = NoCPUReg)
391 : list_(reg1.Bit() | reg2.Bit() | reg3.Bit() | reg4.Bit()),
393 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
H A Dassembler-arm64.cc213 Register reg3, Register reg4) {
214 CPURegList regs(reg1, reg2, reg3, reg4);
228 const CPURegister& reg3, const CPURegister& reg4,
237 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
265 const CPURegister& reg3, const CPURegister& reg4,
272 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
212 GetAllocatableRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4) argument
227 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
264 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) argument
/external/v8/src/arm/
H A Dmacro-assembler-arm.cc3712 Register reg4,
3719 if (reg4.is_valid()) regs |= reg4.bit();
3738 Register reg4,
3744 reg3.is_valid() + reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
3751 if (reg4.is_valid()) regs |= reg4.bit();
3709 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
3735 AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6, Register reg7, Register reg8) argument
H A Dmacro-assembler-arm.h67 Register reg4 = no_reg,
76 Register reg4 = no_reg,
/external/v8/src/ppc/
H A Dmacro-assembler-ppc.cc4238 Register reg4, Register reg5,
4244 if (reg4.is_valid()) regs |= reg4.bit();
4260 bool AreAliased(Register reg1, Register reg2, Register reg3, Register reg4, argument
4264 reg4.is_valid() + reg5.is_valid() + reg6.is_valid() +
4272 if (reg4.is_valid()) regs |= reg4.bit();
4237 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) argument
H A Dmacro-assembler-ppc.h61 Register reg4 = no_reg,
68 Register reg4 = no_reg, Register reg5 = no_reg,
/external/elfutils/libdw/
H A Dknown-dwarf.h524 DWARF_ONE_KNOWN_DW_OP (reg4, DW_OP_reg4) \
/external/v8/src/full-codegen/
H A Dfull-codegen.h305 void PushOperands(Register reg1, Register reg2, Register reg3, Register reg4);

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