/external/llvm/lib/Target/ARM/ |
H A D | ARMTargetTransformInfo.cpp | 107 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 108 { ISD::ZERO_EXTEND, MVT::v2i64, MVT::v2i32, 1 }, 136 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 137 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 161 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 162 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 168 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 169 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 171 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, 172 { ISD::FP_TO_UINT, MVT::v2i32, MV [all...] |
H A D | ARMISelDAGToDAG.cpp | 1832 case MVT::v2i32: OpcodeIndex = 2; break; 1972 case MVT::v2i32: OpcodeIndex = 2; break; 2136 case MVT::v2i32: OpcodeIndex = 2; break; 2250 case MVT::v2i32: OpcodeIndex = 2; break; 3072 case MVT::v2i32: Opc = ARM::VTRNd32; break; 3093 case MVT::v2i32: Opc = ARM::VTRNd32; break; 3113 case MVT::v2i32: Opc = ARM::VTRNd32; break;
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H A D | ARMISelLowering.cpp | 154 addTypeForNEON(VT, MVT::f64, MVT::v2i32); 468 addDRTypeForNEON(MVT::v2i32); 578 setOperationAction(ISD::CTPOP, MVT::v2i32, Custom); 591 setOperationAction(ISD::CTTZ, MVT::v2i32, Custom); 601 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i32, Custom); 635 MVT::v2i32}) { 1088 case MVT::v2i32: case MVT::v1i64: case MVT::v2f32: 4256 SDValue Mask = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v2i32, 4258 EVT OpVT = (VT == MVT::f32) ? MVT::v2i32 : MVT::v1i64; 4510 EVT VmovVT = VT.is128BitVector() ? MVT::v4i32 : MVT::v2i32; [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
H A D | ValueTypes.h | 63 v2i32 = 21, // 2 x i32 enumerator in enum:llvm::MVT::SimpleValueType 199 case v2i32: 234 case v2i32: 265 case v2i32: 352 if (NumElements == 2) return MVT::v2i32; 433 case 2: return MVT::v2i32; 488 return (V == MVT::v8i8 || V==MVT::v4i16 || V==MVT::v2i32 ||
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/external/clang/test/CodeGen/ |
H A D | systemz-abi-vector.c | 22 typedef __attribute__((vector_size(8))) int v2i32; typedef 86 v2i32 pass_v2i32(v2i32 arg) { return arg; }
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H A D | x86_64-arguments.c | 290 typedef unsigned v2i32 __attribute((__vector_size__(8))); typedef 291 v2i32 f36(v2i32 arg) { return arg; }
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/external/llvm/include/llvm/CodeGen/ |
H A D | MachineValueType.h | 88 v2i32 = 39, // 2 x i32 242 SimpleTy == MVT::v2i32 || SimpleTy == MVT::v1i64 || 343 case v2i32: 414 case v2i32: 473 case v2i32: 625 if (NumElements == 2) return MVT::v2i32;
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcISelDAGToDAG.cpp | 236 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32); 240 SDValue RegCopy = CurDAG->getCopyFromReg(Chain, dl, GPVR, MVT::v2i32, 269 TargetOpcode::REG_SEQUENCE, dl, MVT::v2i32, 283 PairedReg = CurDAG->getRegister(GPVR, MVT::v2i32);
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H A D | SparcISelLowering.cpp | 238 assert(VA.getLocVT() == MVT::v2i32); 239 // Legalize ret v2i32 -> ret 2 x i32 (Basically: do what would 417 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); 469 assert(VA.getValVT() == MVT::f64 || VA.getValVT() == MVT::v2i32); 840 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); 860 // TODO: The f64 -> v2i32 conversion is super-inefficient for 864 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::v2i32, Arg); 1000 if (RVLocs[i].getLocVT() == MVT::v2i32) { 1001 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32); 1006 Vec = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v2i32, Ve [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelDAGToDAG.cpp | 490 case MVT::v2i32: 2756 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { 2783 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { 2810 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { 2837 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { 2864 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { 2891 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { 2918 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { 2945 } else if (VT == MVT::v2i32 || VT == MVT::v2f32) { 2972 } else if (VT == MVT::v2i32 || V [all...] |
H A D | AArch64TargetTransformInfo.cpp | 215 { ISD::SINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 218 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 1 }, 249 { ISD::SINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 252 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 2 }, 256 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f32, 1 }, 259 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 263 // Complex, from v2f32: legal type is v2i32 (no cost) or v2i64 (1 ext). 277 // Complex, from v2f64: legal type is v2i32, 1 narrowing => ~2. 278 { ISD::FP_TO_SINT, MVT::v2i32, MVT::v2f64, 2 }, 281 { ISD::FP_TO_UINT, MVT::v2i32, MV [all...] |
H A D | AArch64ISelLowering.cpp | 88 addDRTypeForNEON(MVT::v2i32); 418 // load, floating-point truncating stores, or v2i32->v2i16 truncating store. 570 setOperationAction(ISD::SINT_TO_FP, MVT::v2i32, Custom); 571 setOperationAction(ISD::UINT_TO_FP, MVT::v2i32, Custom); 584 setOperationAction(ISD::CTTZ, MVT::v2i32, Expand); 599 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Expand); 637 AddPromotedToType(ISD::LOAD, VT, MVT::v2i32); 640 AddPromotedToType(ISD::STORE, VT, MVT::v2i32); 719 addTypeForNEON(VT, MVT::v2i32); 2100 return MVT::v2i32; [all...] |
/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_shader_internal.h | 154 LLVMTypeRef v2i32; member in struct:si_shader_context
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/external/llvm/lib/Target/AMDGPU/ |
H A D | AMDGPUISelLowering.cpp | 75 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32); 87 AddPromotedToType(ISD::LOAD, MVT::i64, MVT::v2i32); 93 AddPromotedToType(ISD::LOAD, MVT::f64, MVT::v2i32); 160 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32); 172 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32); 178 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32); 183 setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom); 184 setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom); 201 setTruncStoreAction(MVT::v2i64, MVT::v2i32, Expand); 270 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custo [all...] |
H A D | SIISelLowering.cpp | 65 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass); 83 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); 89 setOperationAction(ISD::STORE, MVT::v2i32, Custom); 115 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand); 491 return MVT::v2i32; 1504 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture); 2097 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1)); 2098 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2)); 2110 SDValue Res = DAG.getBuildVector(MVT::v2i32, DL, {Lo, Hi}); 2266 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, [all...] |
H A D | R600ISelLowering.cpp | 39 addRegisterClass(MVT::v2i32, &AMDGPU::R600_Reg64RegClass); 47 setOperationAction(ISD::LOAD, MVT::v2i32, Custom); 67 setLoadExtAction(ISD::EXTLOAD, MVT::v2i32, MVT::v2i1, Expand); 68 setLoadExtAction(ISD::SEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); 69 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand); 78 setOperationAction(ISD::STORE, MVT::v2i32, Custom); 85 setTruncStoreAction(MVT::v2i32, MVT::v2i1, Expand); 111 setOperationAction(ISD::SETCC, MVT::v2i32, Expand); 130 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 159 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Expan [all...] |
/external/swiftshader/third_party/LLVM/lib/VMCore/ |
H A D | ValueTypes.cpp | 129 case MVT::v2i32: return "v2i32"; 176 case MVT::v2i32: return VectorType::get(Type::getInt32Ty(Context), 2);
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/external/llvm/lib/IR/ |
H A D | ValueTypes.cpp | 171 case MVT::v2i32: return "v2i32"; 249 case MVT::v2i32: return VectorType::get(Type::getInt32Ty(Context), 2);
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.cpp | 242 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) { 409 } else if (LocVT == MVT::v8i8 || LocVT == MVT::v4i16 || LocVT == MVT::v2i32) { 1268 SDValue LX = DAG.getNode(ExtOpc, dl, MVT::v2i32, LHS); 1269 SDValue RX = DAG.getNode(ExtOpc, dl, MVT::v2i32, RHS); 1309 SDValue X1 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op1); 1310 SDValue X2 = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v2i32, Op2); 1311 SDValue SL = DAG.getNode(ISD::VSELECT, DL, MVT::v2i32, PredOp, X1, X2); 1746 addRegisterClass(MVT::v2i32, &Hexagon::DoubleRegsRegClass); 1925 promoteLdStType(MVT::v2i32, MVT::i64); 1977 MVT::v2i32, MV [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
H A D | ARMISelDAGToDAG.cpp | 1575 case MVT::v2i32: OpcodeIndex = 2; break; 1703 case MVT::v2i32: OpcodeIndex = 2; break; 1857 case MVT::v2i32: OpcodeIndex = 2; break; 1969 case MVT::v2i32: OpcodeIndex = 2; break; 2652 case MVT::v2i32: Opc = ARM::VZIPd32; break; 2671 case MVT::v2i32: Opc = ARM::VUZPd32; break; 2690 case MVT::v2i32: Opc = ARM::VTRNd32; break;
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/external/llvm/lib/Target/X86/ |
H A D | X86TargetTransformInfo.cpp | 433 // 64-bit packed integer vectors (v2i32) are promoted to type v2i64. 598 { ISD::UINT_TO_FP, MVT::v2f32, MVT::v2i32, 2 }, 599 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 1 }, 610 { ISD::FP_TO_UINT, MVT::v2i32, MVT::v2f32, 1 }, 695 { ISD::UINT_TO_FP, MVT::v2f64, MVT::v2i32, 6 },
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/external/llvm/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 99 case MVT::v2i32: return "MVT::v2i32";
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/external/swiftshader/third_party/LLVM/utils/TableGen/ |
H A D | CodeGenTarget.cpp | 78 case MVT::v2i32: return "MVT::v2i32";
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/external/mesa3d/src/amd/common/ |
H A D | ac_nir_to_llvm.c | 97 LLVMTypeRef v2i32; member in struct:nir_to_llvm_context 435 arg_types[arg_idx++] = ctx->v2i32; /* persp sample */ 436 arg_types[arg_idx++] = ctx->v2i32; /* persp center */ 437 arg_types[arg_idx++] = ctx->v2i32; /* persp centroid */ 439 arg_types[arg_idx++] = ctx->v2i32; /* linear sample */ 440 arg_types[arg_idx++] = ctx->v2i32; /* linear center */ 441 arg_types[arg_idx++] = ctx->v2i32; /* linear centroid */ 555 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
H A D | SystemZISelDAGToDAG.cpp | 695 ResVT = MVT::v2i32;
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