Searched refs:vldr (Results 1 - 25 of 29) sorted by relevance

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/external/llvm/test/MC/ARM/
H A Ddirective-fpu-instrs.s5 vldr d21, [r7, #296] label
13 vldr d21, [r7, #296] label
H A Dsimple-fp-encoding.s228 @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
229 @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
230 @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
232 vldr.64 d17, [r0]
233 vldr.i32 s0, [lr]
234 vldr.d d0, [lr]
236 @ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
237 @ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
238 vldr.64 d1, [r2, #32]
239 vldr
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H A Dbig-endian-arm-fixup.s47 vldr d0, arm_pcrel_10_label+16
H A Dfullfp16.s221 vldr.16 s1, [pc, #6]
222 vldr.16 s2, [pc, #510]
223 vldr.16 s3, [pc, #-510]
224 vldr.16 s4, [r4, #-18]
225 @ ARM: vldr.16 s1, [pc, #6] @ encoding: [0x03,0x09,0xdf,0xed]
226 @ ARM: vldr.16 s2, [pc, #510] @ encoding: [0xff,0x19,0x9f,0xed]
227 @ ARM: vldr.16 s3, [pc, #-510] @ encoding: [0xff,0x19,0x5f,0xed]
228 @ ARM: vldr.16 s4, [r4, #-18] @ encoding: [0x09,0x29,0x14,0xed]
229 @ THUMB: vldr.16 s1, [pc, #6] @ encoding: [0xdf,0xed,0x03,0x09]
230 @ THUMB: vldr
[all...]
H A Dfullfp16-neg.s164 vldr.16 s1, [pc, #6]
165 vldr.16 s2, [pc, #510]
166 vldr.16 s3, [pc, #-510]
167 vldr.16 s4, [r4, #-18]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
H A Dsimple-fp-encoding.s175 @ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
176 vldr.64 d17, [r0]
178 @ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
179 @ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
180 vldr.64 d1, [r2, #32]
181 vldr.64 d1, [r2, #-32]
183 @ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed]
184 vldr.64 d2, [r3]
186 @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
187 @ CHECK: vldr
[all...]
/external/capstone/suite/MC/ARM/
H A Dsimple-fp-encoding.s.cs89 0x00,0x1b,0xd0,0xed = vldr d17, [r0]
90 0x00,0x0a,0x9e,0xed = vldr s0, [lr]
91 0x00,0x0b,0x9e,0xed = vldr d0, [lr]
92 0x08,0x1b,0x92,0xed = vldr d1, [r2, #32]
93 0x08,0x1b,0x12,0xed = vldr d1, [r2, #-32]
94 0x00,0x2b,0x93,0xed = vldr d2, [r3]
95 0x00,0x3b,0x9f,0xed = vldr d3, [pc]
96 0x00,0x3b,0x9f,0xed = vldr d3, [pc]
97 0x00,0x3b,0x1f,0xed = vldr d3, [pc, #-0]
98 0x00,0x6a,0xd0,0xed = vldr s1
[all...]
/external/v8/src/crankshaft/arm/
H A Dlithium-gap-resolver-arm.cc169 __ vldr(kScratchDoubleReg, cgen_->ToMemOperand(source));
225 __ vldr(kScratchDoubleReg.low(), source_operand);
275 __ vldr(cgen_->ToDoubleRegister(destination), source_operand);
282 __ vldr(kScratchDoubleReg, source_operand);
286 __ vldr(kScratchDoubleReg, source_operand);
H A Dlithium-codegen-arm.cc92 __ vldr(DoubleRegister::from_code(save_iterator.Current()),
456 // TODO(regis): Why is vldr not taking a MemOperand?
457 // __ vldr(dbl_scratch, ToMemOperand(op));
459 __ vldr(dbl_scratch, mem_op.rn(), mem_op.offset());
2053 __ vldr(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset));
2139 __ vldr(dbl_scratch, FieldMemOperand(reg, HeapNumber::kValueOffset));
2628 __ vldr(result, FieldMemOperand(object, offset));
2737 __ vldr(double_scratch0().low(), scratch0(), base_offset);
2740 __ vldr(result, scratch0(), base_offset);
2818 __ vldr(resul
[all...]
/external/v8/src/arm/
H A Ddeoptimizer-arm.cc200 __ vldr(d0, sp, src_offset);
273 __ vldr(reg, r1, src_offset);
H A Dcode-stubs-arm.cc93 __ vldr(double_scratch, MemOperand(input_reg, double_offset));
316 __ vldr(d6, rhs, HeapNumber::kValueOffset - kHeapObjectTag);
341 __ vldr(d7, lhs, HeapNumber::kValueOffset - kHeapObjectTag);
409 __ vldr(d6, rhs, HeapNumber::kValueOffset - kHeapObjectTag);
410 __ vldr(d7, lhs, HeapNumber::kValueOffset - kHeapObjectTag);
696 __ vldr(double_exponent,
1985 __ vldr(d1, r2, HeapNumber::kValueOffset);
1995 __ vldr(d0, r2, HeapNumber::kValueOffset);
H A Dassembler-arm.h1094 void vldr(const DwVfpRegister dst,
1098 void vldr(const DwVfpRegister dst,
1102 void vldr(const SwVfpRegister dst,
1106 void vldr(const SwVfpRegister dst,
H A Dassembler-arm.cc511 // vldr dd, [pc, #offset]
514 // vldr dd, [pp, #offset]
816 // vldr<cond> <Dd>, [pc +/- offset_10].
823 // vldr<cond> <Dd>, [pp +/- offset_10].
2399 void Assembler::vldr(const DwVfpRegister dst, function in class:v8::internal::Assembler
2435 void Assembler::vldr(const DwVfpRegister dst, function in class:v8::internal::Assembler
2443 vldr(dst, ip, 0, cond);
2445 vldr(dst, operand.rn(), operand.offset(), cond);
2450 void Assembler::vldr(const SwVfpRegister dst, function in class:v8::internal::Assembler
2484 void Assembler::vldr(cons function in class:v8::internal::Assembler
[all...]
H A Dmacro-assembler-arm.cc1133 vldr(SwVfpRegister::from_code(dst_code), src);
2553 vldr(double_scratch,
/external/valgrind/none/tests/arm/
H A Dvfp.stdout.exp871 vldr d9, [r6, #+4] :: Dd 0x0000011a 0x00000dd3 *(int*) (Rn + shift) 0x0dd3
872 vldr d16, [r9, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1
873 vldr d30, [r12] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2
874 vldr d22, [r9, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a
875 vldr d29, [r2, #-8] :: Dd 0x00000bb1 0x00000aa0 *(int*) (Rn + shift) 0x0aa0
876 vldr d8, [r8, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a
877 vldr d11, [r12, #-4] :: Dd 0x00000cc2 0x00000bb1 *(int*) (Rn + shift) 0x0bb1
878 vldr d18, [r3] :: Dd 0x00000dd3 0x00000cc2 *(int*) (Rn + shift) 0x0cc2
879 vldr d5, [r10, #+8] :: Dd 0x0000022b 0x0000011a *(int*) (Rn + shift) 0x011a
880 vldr d1
[all...]
/external/v8/src/compiler/arm/
H A Dcode-generator-arm.cc361 __ vldr(result, i.InputOffset(2)); \
1406 __ vldr(i.OutputFloatRegister(), i.InputOffset());
1415 __ vldr(i.OutputDoubleRegister(), i.InputOffset());
2421 __ vldr(g.ToDoubleRegister(destination), src);
2438 __ vldr(temp, src);
2442 __ vldr(temp, src);
2489 __ vldr(temp_1, dst);
2504 __ vldr(src, dst);
2545 __ vldr(kScratchDoubleReg, dst);
2546 __ vldr(kDoubleRegZer
[all...]
/external/vixl/src/aarch32/
H A Dassembler-aarch32.h4680 void vldr(Condition cond, DataType dt, DRegister rd, Location* location);
4686 void vldr(DataType dt, DRegister rd, Location* location) { function in class:vixl::aarch32::Assembler
4687 vldr(al, dt, rd, location);
4689 void vldr(DRegister rd, Location* location) { function in class:vixl::aarch32::Assembler
4690 vldr(al, Untyped64, rd, location);
4692 void vldr(Condition cond, DRegister rd, Location* location) { function in class:vixl::aarch32::Assembler
4693 vldr(cond, Untyped64, rd, location);
4696 void vldr(Condition cond,
4700 void vldr(DataType dt, DRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
4701 vldr(a
4703 void vldr(DRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
4706 void vldr(Condition cond, DRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
4716 void vldr(DataType dt, SRegister rd, Location* location) { function in class:vixl::aarch32::Assembler
4719 void vldr(SRegister rd, Location* location) { function in class:vixl::aarch32::Assembler
4722 void vldr(Condition cond, SRegister rd, Location* location) { function in class:vixl::aarch32::Assembler
4730 void vldr(DataType dt, SRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
4733 void vldr(SRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
4736 void vldr(Condition cond, SRegister rd, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
[all...]
H A Ddisasm-aarch32.h1906 void vldr(Condition cond, DataType dt, DRegister rd, Location* location);
1908 void vldr(Condition cond,
1913 void vldr(Condition cond, DataType dt, SRegister rd, Location* location);
1915 void vldr(Condition cond,
H A Dmacro-assembler-aarch32.cc2106 "The MacroAssembler does not convert vldr or vstr with a PC base "
2112 // vldr.32 s0, [r1, 12345]! will translate into
2114 // vldr.32 s0, [r1]
2128 // vldr.32 s0, [r1, 12345] will translate into
2130 // vldr.32 s0, [ip]
2144 // vldr.32 s0, [r1], imm32 will translate into
2145 // vldr.32 s0, [r1]
2179 "The MacroAssembler does not convert vldr or vstr with a PC base "
2185 // vldr.64 d0, [r1, 12345]! will translate into
2187 // vldr
[all...]
H A Ddisasm-aarch32.cc4997 void Disassembler::vldr(Condition cond, function in class:vixl::aarch32::Disassembler
5009 void Disassembler::vldr(Condition cond, function in class:vixl::aarch32::Disassembler
5019 void Disassembler::vldr(Condition cond, function in class:vixl::aarch32::Disassembler
5031 void Disassembler::vldr(Condition cond, function in class:vixl::aarch32::Disassembler
[all...]
/external/boringssl/src/crypto/chacha/asm/
H A Dchacha-armv4.pl781 vldr $t0#lo,[sp,#4*(16+0)] @ one
786 vldr $t1#lo,[sp,#4*(16+2)] @ two
823 vldr $t0#lo,[sp,#4*(16+4)] @ four
832 vldr $t0#lo,[sp,#4*(16+0)] @ one
/external/boringssl/ios-arm/crypto/chacha/
H A Dchacha-armv4.S1107 vldr d24,[sp,#4*(16+0)] @ one
1112 vldr d26,[sp,#4*(16+2)] @ two
1149 vldr d24,[sp,#4*(16+4)] @ four
1158 vldr d24,[sp,#4*(16+0)] @ one
/external/boringssl/linux-arm/crypto/chacha/
H A Dchacha-armv4.S1104 vldr d24,[sp,#4*(16+0)] @ one
1109 vldr d26,[sp,#4*(16+2)] @ two
1146 vldr d24,[sp,#4*(16+4)] @ four
1155 vldr d24,[sp,#4*(16+0)] @ one
/external/v8/src/builtins/arm/
H A Dbuiltins-arm.cc139 __ vldr(d1, FieldMemOperand(r5, HeapNumber::kValueOffset));
179 __ vldr(d1, FieldMemOperand(r5, HeapNumber::kValueOffset));
185 __ vldr(d2, FieldMemOperand(r2, HeapNumber::kValueOffset));
213 __ vldr(d1, FieldMemOperand(r5, HeapNumber::kValueOffset));
/external/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc4119 // problem technically exists for the other loads, but vldr is particularly
4120 // badly affected because vldr cannot set the low bits in its offset mask,
4127 // vldr d0, [r8, #48]
4132 // vldr d0, [ip, #48]
6649 "vldr",
6651 vldr(al, Untyped64, d0, &label));
6654 "vldr",
6656 vldr(al, Untyped32, s0, &label));
6737 "vldr",
6739 vldr(a
[all...]

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