/external/mesa3d/src/gallium/winsys/radeon/drm/ |
H A D | radeon_drm_surface.c | 75 level_drm->nblk_x = level_ws->nblk_x; 77 level_drm->pitch_bytes = level_ws->nblk_x * bpe; 87 level_ws->nblk_x = level_drm->nblk_x; 90 assert(level_drm->nblk_x * bpe == level_drm->pitch_bytes);
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/external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
H A D | radv_amdgpu_surface.c | 187 AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x; 189 AddrSurfInfoIn->basePitch = surf->level[0].nblk_x; 209 surf_level->nblk_x = AddrSurfInfoOut->pitch; 500 if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
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/external/libdrm/radeon/ |
H A D | radeon_surface.h | 75 uint32_t nblk_x; member in struct:radeon_surface_level
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H A D | radeon_surface.c | 179 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; 184 if (surflevel->nblk_x < xalign || surflevel->nblk_y < yalign) { 189 surflevel->nblk_x = ALIGN(surflevel->nblk_x, xalign); 194 surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples; 588 surflevel->nblk_x = (surflevel->npix_x + surf->blk_w - 1) / surf->blk_w; 593 if (surflevel->nblk_x < mtilew || surflevel->nblk_y < mtileh) { 598 surflevel->nblk_x = ALIGN(surflevel->nblk_x, mtilew); 603 mtile_pr = surflevel->nblk_x / mtile [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | radeon_vce_40_2_2.c | 97 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch 98 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch 327 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch 328 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
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H A D | radeon_vce_50.c | 134 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch 135 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
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H A D | r600_texture.c | 186 rtex->surface.level[level].nblk_x + 266 pitch_in_bytes_override != surface->level[0].nblk_x * bpe) { 270 surface->level[0].nblk_x = pitch_in_bytes_override / bpe; 297 metadata->stride = surface->level[0].nblk_x * surface->bpe; 554 rtex->surface.level[0].nblk_x * 636 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64; 641 out->pitch_in_pixels = fmask.level[0].nblk_x; 951 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, " 958 rtex->surface.level[i].nblk_x, 969 "npix_y=%u, npix_z=%u, nblk_x [all...] |
H A D | radeon_vce.c | 227 unsigned pitch = align(enc->luma->level[0].nblk_x * enc->luma->bpe, 128); 459 cpb_size = align(tmp_surf->level[0].nblk_x * tmp_surf->bpe, 128);
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H A D | radeon_vce_52.c | 180 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch 181 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch 247 RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch 248 RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
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H A D | radeon_winsys.h | 292 uint16_t nblk_x; member in struct:radeon_surf_level
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H A D | radeon_uvd.c | 1356 msg->body.decode.dt_pitch = luma->level[0].nblk_x * luma->bpe;
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/external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
H A D | amdgpu_surface.c | 175 AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x; 177 AddrSurfInfoIn->basePitch = surf->level[0].nblk_x; 194 surf_level->nblk_x = AddrSurfInfoOut->pitch; 543 if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
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/external/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_dma.c | 170 slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x * 271 dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe; 272 src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
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H A D | cik_sdma.c | 164 unsigned dst_pitch = rdst->surface.level[dst_level].nblk_x; 165 unsigned src_pitch = rsrc->surface.level[src_level].nblk_x;
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H A D | si_state.c | 2313 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); 2323 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) | 2325 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x * 2546 pitch_tile_max = level_info->nblk_x / 8 - 1; 2547 slice_tile_max = level_info->nblk_x *
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H A D | si_descriptors.c | 384 unsigned pitch = base_level_info->nblk_x * block_width;
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/external/mesa3d/src/amd/vulkan/ |
H A D | radv_image.c | 200 unsigned pitch = base_level_info->nblk_x * block_width; 494 out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64; 499 out->pitch_in_pixels = fmask.level[0].nblk_x; 743 image->surface.level[0].nblk_x = create_info->stride / image->surface.bpe;
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H A D | radv_radeon_winsys.h | 162 uint32_t nblk_x; member in struct:radeon_surf_level
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H A D | radv_device.c | 1615 pitch_tile_max = level_info->nblk_x / 8 - 1; 1616 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1; 1836 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) | 1838 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
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/external/mesa3d/src/gallium/drivers/r600/ |
H A D | evergreen_state.c | 754 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format); 1006 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1; 1007 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1214 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0); 1219 surf->db_depth_size = S_028058_PITCH_TILE_MAX(levelinfo->nblk_x / 8 - 1) | 1221 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX(levelinfo->nblk_x * 3377 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8); 3402 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8); 3494 dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe; 3495 src_pitch = rsrc->surface.level[src_level].nblk_x * rsr [all...] |
H A D | r600_state.c | 726 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format); 831 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 832 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 1026 pitch = rtex->surface.level[level].nblk_x / 8 - 1; 1027 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64; 2838 slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8); 2857 slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8); 2949 dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe; 2950 src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
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