Searched defs:CLK_SOURCE_CSITE (Results 1 - 4 of 4) sorted by path

/drivers/clk/tegra/
H A Dclk-tegra-periph.c63 #define CLK_SOURCE_CSITE 0x1d4 macro
496 MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_csite, CLK_IGNORE_UNUSED),
H A Dclk-tegra114.c144 #define CLK_SOURCE_CSITE 0x1d4 macro
1265 readl(clk_base + CLK_SOURCE_CSITE);
1266 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1277 clk_base + CLK_SOURCE_CSITE);
H A Dclk-tegra124.c31 #define CLK_SOURCE_CSITE 0x1d4 macro
1324 readl(clk_base + CLK_SOURCE_CSITE);
1325 writel(3 << 30, clk_base + CLK_SOURCE_CSITE);
1331 clk_base + CLK_SOURCE_CSITE);
H A Dclk-tegra20.c107 #define CLK_SOURCE_CSITE 0x1d4 macro
955 readl(clk_base + CLK_SOURCE_CSITE);
956 writel(3<<30, clk_base + CLK_SOURCE_CSITE);
1005 clk_base + CLK_SOURCE_CSITE);

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