| /drivers/clk/berlin/ |
| H A D | berlin2-div.c | 239 void __iomem *base, const char *name, u8 div_flags,
257 if ((div_flags & BERLIN2_DIV_HAS_GATE) == 0)
259 if ((div_flags & BERLIN2_DIV_HAS_MUX) == 0)
238 berlin2_div_register(const struct berlin2_div_map *map, void __iomem *base, const char *name, u8 div_flags, const char **parent_names, int num_parents, unsigned long flags, spinlock_t *lock) argument
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| H A D | berlin2-div.h | 80 u8 div_flags; member in struct:berlin2_div_data
85 void __iomem *base, const char *name, u8 div_flags,
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| /drivers/clk/hisilicon/ |
| H A D | clk.h | 77 u8 div_flags; member in struct:hisi_divider_clock
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| /drivers/clk/rockchip/ |
| H A D | clk.c | 44 u8 div_shift, u8 div_width, u8 div_flags,
87 div->flags = div_flags;
107 int muxdiv_offset, u8 div_flags,
135 div->flags = div_flags;
237 list->div_flags, list->div_table,
244 list->div_flags, &clk_lock);
252 reg_base, list->muxdiv_offset, list->div_flags,
276 list->div_flags, list->div_table,
41 rockchip_clk_register_branch(const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 mux_shift, u8 mux_width, u8 mux_flags, u8 div_shift, u8 div_width, u8 div_flags, struct clk_div_table *div_table, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) argument
105 rockchip_clk_register_frac_branch(const char *name, const char **parent_names, u8 num_parents, void __iomem *base, int muxdiv_offset, u8 div_flags, int gate_offset, u8 gate_shift, u8 gate_flags, unsigned long flags, spinlock_t *lock) argument
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| H A D | clk.h | 178 u8 div_flags; member in struct:rockchip_clk_branch
200 .div_flags = df, \
218 .div_flags = df, \
236 .div_flags = df, \
276 .div_flags = df, \
291 .div_flags = df, \
323 .div_flags = df, \
338 .div_flags = df, \
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| /drivers/clk/samsung/ |
| H A D | clk.h | 174 * @div_flags: flags for div-type clock.
186 u8 div_flags; member in struct:samsung_div_clock
201 .div_flags = df, \
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| /drivers/clk/tegra/ |
| H A D | clk-tegra-periph.c | 557 u8 div_flags; member in struct:pll_out_data
568 .div_flags = _div_flags | TEGRA_DIVIDER_FIXED |\
666 clk_base + data->offset, 0, data->div_flags,
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| /drivers/clk/ti/ |
| H A D | divider.c | 399 u32 *flags, u8 *div_flags, u8 *width, u8 *shift)
413 *div_flags = 0;
416 *div_flags |= CLK_DIVIDER_ONE_BASED;
419 *div_flags |= CLK_DIVIDER_POWER_OF_TWO;
429 *width = _get_divider_width(node, *table, *div_flags);
397 ti_clk_divider_populate(struct device_node *node, void __iomem **reg, const struct clk_div_table **table, u32 *flags, u8 *div_flags, u8 *width, u8 *shift) argument
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