/drivers/staging/comedi/drivers/ |
H A D | das08_cs.c | 68 unsigned long iobase; local 78 iobase = link->resource[0]->start; 84 return das08_common_attach(dev, iobase);
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H A D | amplc_pci236.c | 100 unsigned long iobase; local 117 iobase = pci_resource_start(pci_dev, 2); 118 return amplc_pc236_common_attach(dev, iobase, pci_dev->irq,
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H A D | dt2817.c | 74 outb(oe, dev->iobase + DT2817_CR); 84 unsigned long iobase = dev->iobase + DT2817_DATA; local 91 outb(s->state & 0xff, iobase + 0); 93 outb((s->state >> 8) & 0xff, iobase + 1); 95 outb((s->state >> 16) & 0xff, iobase + 2); 97 outb((s->state >> 24) & 0xff, iobase + 3); 100 val = inb(iobase + 0); 101 val |= (inb(iobase + 1) << 8); 102 val |= (inb(iobase [all...] |
H A D | ni_atmio.c | 306 unsigned long iobase; local 315 iobase = it->options[0]; 318 if (iobase == 0) { 323 iobase = pnp_port_start(isapnp_dev, 0); 328 ret = comedi_request_region(dev, iobase, 0x20);
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H A D | addi_watchdog.c | 39 unsigned long iobase; member in struct:addi_watchdog_private 65 outl(reload, spriv->iobase + ADDI_WDOG_RELOAD_REG); 78 outl(spriv->wdog_ctrl, spriv->iobase + ADDI_WDOG_CTRL_REG); 92 data[i] = inl(spriv->iobase + ADDI_WDOG_STATUS_REG); 113 spriv->iobase + ADDI_WDOG_CTRL_REG); 119 void addi_watchdog_reset(unsigned long iobase) argument 121 outl(0x0, iobase + ADDI_WDOG_CTRL_REG); 122 outl(0x0, iobase + ADDI_WDOG_RELOAD_REG); 126 int addi_watchdog_init(struct comedi_subdevice *s, unsigned long iobase) argument 134 spriv->iobase [all...] |
H A D | amplc_pc236_common.c | 145 int amplc_pc236_common_attach(struct comedi_device *dev, unsigned long iobase, argument 151 dev->iobase = iobase;
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H A D | pcl724.c | 84 unsigned long iobase) 86 int movport = I8255_SIZE * (iobase >> 12); 88 iobase &= 0x0fff; 90 outb(port + movport, iobase); 92 outb(data, iobase + 1); 95 return inb(iobase + 1); 103 unsigned long iobase; local 130 iobase = dev->iobase + (i * 0x1000); 132 iobase); 82 pcl724_8255mapped_io(struct comedi_device *dev, int dir, int port, int data, unsigned long iobase) argument [all...] |
H A D | 8255.c | 58 subdev_8255_init(device, subdevice, io_function, iobase) 63 access. io_function will be called with the value of iobase 66 and the I/O port base for iobase, and an internal function will 91 outb(data, dev->iobase + regbase + port); 94 return inb(dev->iobase + regbase + port); 248 unsigned long iobase; local 253 iobase = it->options[i]; 254 if (!iobase) 268 iobase = it->options[i]; 271 * __comedi_request_region() does not set dev->iobase [all...] |
/drivers/dma/ioat/ |
H A D | pci.c | 138 alloc_ioatdma(struct pci_dev *pdev, void __iomem *iobase) argument 146 d->reg_base = iobase;
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/drivers/char/tpm/ |
H A D | tpm_atmel.h | 29 #define atmel_getb(chip, offset) readb(chip->vendor->iobase + offset); 30 #define atmel_putb(val, chip, offset) writeb(val, chip->vendor->iobase + offset) 34 static inline void atmel_put_base_addr(void __iomem *iobase) argument 36 iounmap(iobase); 111 static inline void atmel_put_base_addr(void __iomem *iobase) argument
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H A D | tpm_atmel.c | 50 status = ioread8(chip->vendor.iobase + 1); 55 *buf++ = ioread8(chip->vendor.iobase); 66 status = ioread8(chip->vendor.iobase + 1); 77 status = ioread8(chip->vendor.iobase + 1); 82 *buf++ = ioread8(chip->vendor.iobase); 86 status = ioread8(chip->vendor.iobase + 1); 103 iowrite8(buf[i], chip->vendor.iobase); 111 iowrite8(ATML_STATUS_ABORT, chip->vendor.iobase + 1); 116 return ioread8(chip->vendor.iobase + 1); 144 atmel_put_base_addr(chip->vendor.iobase); 163 void __iomem *iobase = NULL; local [all...] |
/drivers/clocksource/ |
H A D | dw_apb_timer_of.c | 64 void __iomem *iobase; local 72 timer_get_base_and_rate(event_timer, &iobase, &rate); 74 ced = dw_apb_clockevent_init(0, event_timer->name, 300, iobase, irq, 87 void __iomem *iobase; local 91 timer_get_base_and_rate(source_timer, &iobase, &rate); 93 cs = dw_apb_clocksource_init(300, source_timer->name, iobase, rate); 105 sched_io_base = iobase + 0x04;
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/drivers/irqchip/ |
H A D | irq-dw-apb-ictl.c | 60 void __iomem *iobase; local 82 iobase = ioremap(r.start, resource_size(&r)); 83 if (!iobase) { 97 writel(~0, iobase + APB_INT_MASK_L); 98 writel(~0, iobase + APB_INT_MASK_H); 99 writel(~0, iobase + APB_INT_ENABLE_L); 100 writel(~0, iobase + APB_INT_ENABLE_H); 102 reg = readl(iobase + APB_INT_ENABLE_H); 106 nrirqs = fls(readl(iobase + APB_INT_ENABLE_L)); 126 gc->reg_base = iobase; [all...] |
/drivers/mtd/maps/ |
H A D | l440gx.c | 21 static u32 iobase; variable 22 #define IOBASE iobase 90 /* Setup the pm iobase resource 97 pm_iobase->name = "pm iobase"; 103 pci_read_config_dword(pm_dev, 0x40, &iobase); 104 iobase &= ~1; 105 pm_iobase->start += iobase & ~1; 106 pm_iobase->end += iobase & ~1; 114 printk(KERN_WARNING "Could not allocate pm iobase resource\n"); 119 /* Set the iobase */ [all...] |
/drivers/scsi/ |
H A D | qlogicfas.c | 138 static int iobase[MAX_QLOGICFAS]; variable 140 module_param_array(iobase, int, NULL, 0); 142 MODULE_PARM_DESC(iobase, "I/O address"); 152 shost = __qlogicfas_detect(sht, iobase[num], irq[num]); 205 "I/O address and IRQ using iobase= and irq= "
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/drivers/ata/ |
H A D | pata_rb532_cf.c | 50 void __iomem *iobase; member in struct:rb532_cf_info 95 ap->ioaddr.cmd_addr = info->iobase + RB500_CF_REG_BASE; 96 ap->ioaddr.ctl_addr = info->iobase + RB500_CF_REG_CTRL; 97 ap->ioaddr.altstatus_addr = info->iobase + RB500_CF_REG_CTRL; 101 ap->ioaddr.data_addr = info->iobase + RB500_CF_REG_DBUF32; 102 ap->ioaddr.error_addr = info->iobase + RB500_CF_REG_ERR; 153 info->iobase = devm_ioremap_nocache(&pdev->dev, res->start, 155 if (!info->iobase)
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/drivers/isdn/sc/ |
H A D | init.c | 349 sc_adapter[cinst]->iobase = io[b]; 439 static int identify_board(unsigned long rambase, unsigned int iobase) argument 450 rambase, iobase); 455 outb(rambase >> 12, iobase + 0x2c00); 459 pgport = iobase + PG0_OFFSET; 464 pgport = iobase + PG1_OFFSET; 469 pgport = iobase + PG2_OFFSET; 474 pgport = iobase + PG3_OFFSET; 520 outb(0, iobase + 0x400); 526 while ((inb(iobase [all...] |
/drivers/net/wan/ |
H A D | hostess_sv11.c | 188 static struct z8530_dev *sv11_init(int iobase, int irq) argument 196 if (!request_region(iobase, 8, "Comtrol SV11")) { 197 pr_warn("I/O 0x%X already in use\n", iobase); 211 sv->chanA.ctrlio = iobase + 1; 212 sv->chanA.dataio = iobase + 3; 218 outb(0, iobase + 4); /* DMA off */ 241 outb(0x03 | 0x08, iobase + 4); /* DMA on */ 282 netdev->base_addr = iobase; 291 z8530_describe(sv, "I/O", iobase); 306 release_region(iobase, [all...] |
H A D | sealevel.c | 49 int iobase; member in struct:slvl_board 182 static int slvl_setup(struct slvl_device *sv, int iobase, int irq) argument 191 dev->base_addr = iobase; 209 static __init struct slvl_board *slvl_init(int iobase, int irq, argument 219 if (!request_region(iobase, 8, "Sealevel 4021")) { 220 pr_warn("I/O 0x%X already in use\n", iobase); 242 b->iobase = iobase; 249 iobase |= Z8530_PORT_SLEEP; 251 dev->chanA.ctrlio = iobase [all...] |
/drivers/thunderbolt/ |
H A D | nhi.h | 23 void __iomem *iobase; member in struct:tb_nhi
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/drivers/video/ |
H A D | vgastate.c | 34 static inline unsigned char vga_rcrtcs(void __iomem *regbase, unsigned short iobase, argument 37 vga_w(regbase, iobase + 0x4, reg); 38 return vga_r(regbase, iobase + 0x5); 41 static inline void vga_wcrtcs(void __iomem *regbase, unsigned short iobase, argument 44 vga_w(regbase, iobase + 0x4, reg); 45 vga_w(regbase, iobase + 0x5, val); 53 unsigned short iobase; local 57 iobase = (misc & 1) ? 0x3d0 : 0x3b0; 59 vga_r(state->vgabase, iobase + 0xa); 62 vga_r(state->vgabase, iobase 229 unsigned short iobase; local 260 unsigned short iobase; local [all...] |
/drivers/bluetooth/ |
H A D | dtl1_cs.c | 110 static int dtl1_write(unsigned int iobase, int fifo_size, __u8 *buf, int len) argument 115 if (!(inb(iobase + UART_LSR) & UART_LSR_THRE)) 121 outb(buf[actual], iobase + UART_TX); 147 unsigned int iobase = info->p_dev->resource[0]->start; local 161 len = dtl1_write(iobase, 32, skb->data, skb->len); 204 unsigned int iobase; local 213 iobase = info->p_dev->resource[0]->start; 229 *skb_put(info->rx_skb, 1) = inb(iobase + UART_RX); 284 } while (inb(iobase + UART_LSR) & UART_LSR_DR); 291 unsigned int iobase; local 442 unsigned int iobase = info->p_dev->resource[0]->start; local 511 unsigned int iobase = info->p_dev->resource[0]->start; local [all...] |
/drivers/char/pcmcia/ |
H A D | cm4040_cs.c | 141 int iobase = dev->p_dev->resource[0]->start; local 144 if ((xinb(iobase + REG_OFFSET_BUFFER_STATUS) 171 int iobase = dev->p_dev->resource[0]->start; local 178 xoutb(val, iobase + REG_OFFSET_SYNC_CONTROL); 189 int iobase = dev->p_dev->resource[0]->start; local 192 if ((xinb(iobase + REG_OFFSET_BUFFER_STATUS) 219 int iobase = dev->p_dev->resource[0]->start; local 252 dev->r_buf[i] = xinb(iobase + REG_OFFSET_BULK_IN); 279 dev->r_buf[i+5] = xinb(iobase + REG_OFFSET_BULK_IN); 311 uc = xinb(iobase [all...] |
/drivers/clk/ti/ |
H A D | clk-dra7-atl.c | 58 void __iomem *iobase; member in struct:dra7_atl_clock_info 68 __raw_writel(val, cinfo->iobase + reg); 73 return __raw_readl(cinfo->iobase + reg); 229 cinfo->iobase = of_iomap(node, 0);
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/drivers/i2c/busses/ |
H A D | i2c-xlr.c | 68 u32 __iomem *iobase; member in struct:xlr_i2c_private 81 xlr_i2c_wreg(priv->iobase, XLR_I2C_ADDR, offset); 82 xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr); 83 xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG, XLR_I2C_CFG_ADDR); 84 xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1); 92 xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, 95 xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[pos]); 96 xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, 102 i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS); 108 xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOU [all...] |