Searched refs:t1 (Results 1 - 25 of 106) sorted by relevance

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/arch/mips/kernel/
H A Dr4k_switch.S41 mfc0 t1, CP0_STATUS
42 LONG_S t1, THREAD_STATUS(a0)
63 li t1, ~ST0_CU1
64 and t0, t0, t1
73 cfc1 t1, fcr31
77 sw t1, THREAD_FCR31(a0)
81 fpu_save_double a0 t0 t1 # c0_status passed in t0
82 # clobbers t1
99 set_saved_sp t0, t1, t2
100 mfc0 t1, CP0_STATU
[all...]
H A Dcps-vec.S94 li t1, 2
95 sllv t0, t1, t0
98 _EXT t1, v0, MIPS_CONF1_IS_SHF, MIPS_CONF1_IS_SZ
99 xori t2, t1, 0x7
102 addi t1, t1, 1
103 sllv t1, t3, t1
104 1: /* At this point t1 == I-cache sets per way */
107 mul t1, t
[all...]
H A Docteon_switch.S26 mfc0 t1, CP0_STATUS
27 LONG_S t1, THREAD_STATUS(a0)
36 li t1, _TIF_USEDFPU
37 and t2, t0, t1
39 nor t1, zero, t1
41 and t0, t0, t1
48 li t1, ~ST0_CU1
49 and t0, t0, t1
54 fpu_save_double a0 t0 t1 # c0_statu
[all...]
H A Dr2300_switch.S48 mfc0 t1, CP0_STATUS
49 sw t1, THREAD_STATUS(a0)
61 li t1, ~ST0_CU1
62 and t0, t0, t1
82 addiu t1, $28, _THREAD_SIZE - 32
83 sw t1, kernelsp
85 mfc0 t1, CP0_STATUS /* Do we really need this? */
87 and t1, a3
91 or a2, t1
101 fpu_save_single a0, t1 # clobber
[all...]
/arch/alpha/include/uapi/asm/
H A Dswab.h26 __u64 t0, t1, t2, t3; local
29 t1 = __kernel_inswl(x, 3); /* t1 : 000000CCDD000000 */
30 t1 |= t0; /* t1 : 000000CCDDAABBCC */
31 t2 = t1 >> 16; /* t2 : 0000000000CCDDAA */
32 t0 = t1 & 0xFF00FF00; /* t0 : 00000000DD00BB00 */
34 t1 = t0 + t3; /* t1 : ssssssssDDCCBBAA */
36 return t1;
[all...]
/arch/mips/include/asm/sibyte/
H A Dboard.h42 #define setleds(t0, t1, c0, c1, c2, c3) \
44 li t1, c0; \
45 sb t1, 0x18(t0); \
46 li t1, c1; \
47 sb t1, 0x10(t0); \
48 li t1, c2; \
49 sb t1, 0x08(t0); \
50 li t1, c3; \
51 sb t1, 0x00(t0)
53 #define setleds(t0, t1, c
[all...]
/arch/x86/purgatory/
H A Dsha256.c50 u32 a, b, c, d, e, f, g, h, t1, t2; local
67 t1 = h + e1(e) + Ch(e, f, g) + 0x428a2f98 + W[0];
68 t2 = e0(a) + Maj(a, b, c); d += t1; h = t1 + t2;
69 t1 = g + e1(d) + Ch(d, e, f) + 0x71374491 + W[1];
70 t2 = e0(h) + Maj(h, a, b); c += t1; g = t1 + t2;
71 t1 = f + e1(c) + Ch(c, d, e) + 0xb5c0fbcf + W[2];
72 t2 = e0(g) + Maj(g, h, a); b += t1; f = t1
[all...]
/arch/alpha/include/asm/
H A Dword-at-a-time.h41 unsigned long t1, t2, t3;
45 t1 = bits & 0xf0;
48 if (t1) t1 = 4;
51 return t1 + t2 + t3;
/arch/mips/netlogic/common/
H A Dreset.S61 mfcr t1, t0
64 or t1, t1, t2
65 mtcr t1, t0
68 mfcr t1, t0
69 ori t1, 0x1000 /* Enable Icache partitioning */
70 mtcr t1, t0
73 lui t1, 0x0100 /* Disable BRU accepting ALU ops */
74 mtcr t1, t0
84 li t1, (
[all...]
H A Dsmpboot.S64 dla t1, nlm_reset_entry
66 dsubu t2, t1
78 move t1, zero
80 ori t1, ST0_KX
82 mtc0 t1, CP0_STATUS
83 PTR_LA t1, nlm_next_sp
84 PTR_L sp, 0(t1)
85 PTR_LA t1, nlm_next_gp
86 PTR_L gp, 0(t1)
113 ADDIU t1, t
[all...]
/arch/mips/include/asm/mach-paravirt/
H A Dkernel-entry-init.h30 slti t1, t0, NR_CPUS variable
31 bnez t1, 1f variable
37 PTR_LA t1, paravirt_smp_sp
39 PTR_ADDU t1, t1, t0 variable
41 PTR_L sp, 0(t1)
44 PTR_LA t1, paravirt_smp_gp
45 PTR_ADDU t1, t1, t0 variable
47 PTR_L gp, 0(t1)
[all...]
/arch/mips/include/asm/mach-ath79/
H A Dkernel-entry-init.h22 li t1, ~CONF_CM_CMASK variable
23 and t0, t1
/arch/parisc/lib/
H A Dfixup.S28 .macro get_fault_ip t1 t2
30 LDREG RT%__per_cpu_offset(%r1),\t1
38 LDREGX \t2(\t1),\t2
40 LDREG RT%exception_data(%r1),\t1
41 /* t1 = &__get_cpu_var(exception_data) */
42 add,l \t1,\t2,\t1
43 /* t1 = t1->fault_ip */
44 LDREG EXCDATA_IP(\t1), \t
[all...]
/arch/alpha/lib/
H A Dev6-stxcpy.S54 t1 == the first source word. */
59 mskqh t1, a1, t3 # U :
60 ornot t1, t2, t2 # E : (stall)
64 or t0, t3, t1 # E : (stall)
69 t1 == a source word not containing a null. */
73 stq_u t1, 0(a0) # L :
78 ldq_u t1, 0(a1) # L : Latency=3
80 cmpbge zero, t1, t8 # E : (3 cycle stall)
85 t1 == the source word containing the null
99 zapnot t1, t
[all...]
H A Dstxcpy.S43 t1 == the first source word. */
48 mskqh t1, a1, t3 # e0 :
49 ornot t1, t2, t2 # .. e1 :
52 or t0, t3, t1 # e0 :
57 t1 == a source word not containing a null. */
60 stq_u t1, 0(a0) # e0 :
62 ldq_u t1, 0(a1) # e0 :
64 cmpbge zero, t1, t8 # e0 (stall)
69 t1 == the source word containing the null
84 zapnot t1, t
[all...]
H A Dstrrchr.S32 cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero
38 andnot t1, t4, t1 # .. e1 : clear garbage from null test
40 bne t1, $eos # .. e1 : did we already hit the terminator?
49 cmpbge zero, t0, t1 # .. e1 : bits set iff byte == zero
51 beq t1, $loop # .. e1 : if we havnt seen a null, loop
55 negq t1, t4 # e0 : isolate first null byte match
56 and t1, t4, t4 # e1 :
73 and t8, 0xcc, t1 # .. e1 :
74 cmovne t1, t
[all...]
H A Dev6-stxncpy.S62 t1 == the first source word. */
67 mskqh t1, a1, t3 # U :
68 ornot t1, t2, t2 # E : (stall)
121 ldq_u t1, 0(a0) # L :
126 zap t1, t8, t1 # .. e1 : clear dst bytes <= null
127 or t0, t1, t0 # e1 : (stall)
153 xor a0, a1, t1 # E :
155 and t1, 7, t1 #
[all...]
/arch/mips/include/asm/mach-ip27/
H A Dkernel-entry-init.h35 * inputs are the text nasid in t1, data nasid in t2.
47 dsll t1, NASID_SHFT # Shift text nasid into place variable
49 or t1, t1, t0 # Physical load address of kernel text variable
51 dsrl t1, 12 # 4K pfn variable
53 dsll t1, 6 # Get pfn into place variable
56 or t0, t0, t1
78 GET_NASID_ASM t1
79 move t2, t1 # text and data are here
87 GET_NASID_ASM t1
90 dsll t1, NASID_SHFT variable
93 lh t1, KV_RO_NASID_OFFSET(t0) variable in typeref:struct:lh
[all...]
/arch/mips/include/asm/
H A Dpm.h67 /* Get address of static suspend state into t1 */
69 la t1, mips_static_suspend_state
80 LONG_S k0, SSS_SEGCTL0(t1)
82 LONG_S k0, SSS_SEGCTL1(t1)
84 LONG_S k0, SSS_SEGCTL2(t1)
87 LONG_S sp, SSS_SP(t1)
98 LONG_L k0, SSS_SEGCTL0(t1)
100 LONG_L k0, SSS_SEGCTL1(t1)
102 LONG_L k0, SSS_SEGCTL2(t1)
107 LONG_L sp, SSS_SP(t1)
[all...]
/arch/mips/include/asm/mach-malta/
H A Dkernel-entry-init.h35 * The following code uses the t0, t1, t2 and ra registers without
47 mfc0 t1, CP0_CONFIG
48 andi t1, 0x7 /* CCA */ variable
49 move t2, t1
50 ins t2, t1, 16, 3 variable
69 ins t0, t1, 16, 3 variable
99 mfc0 t1, CP0_CONFIG
100 bgez t1, 9f variable
/arch/mips/dec/
H A Dint-handler.S132 mfc0 t1,CP0_STATUS
137 and t0,t1 # isolate allowed ones
149 PTR_LA t1,cpu_mask_nr_tbl
150 1: lw t2,(t1)
154 addu t1,2*PTRSIZE # delay slot
159 lw a0,(-PTRSIZE)(t1)
178 andi t1,t0,KN02_IRQ_ALL
188 lw t1,IO_REG_SIMR(t2) # get mask: IOASIC simr
191 1: and t0,t1 # mask out allowed ones
198 PTR_LA t1,asic_mask_nr_tb
[all...]
/arch/ia64/lib/
H A Dcarta_random.S18 #define t1 r17 define
25 pmpyshr2.u t1 = a, seed, 16
27 unpack2.l t0 = t1, t0
36 shr t1 = hi, 15 // t1 = (hi >> 15)
46 add lo = lo, t1
/arch/x86/crypto/
H A Dglue_helper-asm-avx.S54 #define load_ctr_8way(iv, bswap, x0, x1, x2, x3, x4, x5, x6, x7, t0, t1, t2) \
57 vmovdqa bswap, t1; \
61 vpshufb t1, x7, x0; \
65 vpshufb t1, x7, x1; \
67 vpshufb t1, x7, x2; \
69 vpshufb t1, x7, x3; \
71 vpshufb t1, x7, x4; \
73 vpshufb t1, x7, x5; \
75 vpshufb t1, x7, x6; \
78 vpshufb t1, x
[all...]
/arch/mips/lib/
H A Dmemset.S124 1: ori t1, a2, 0x3f /* # of full blocks */
125 xori t1, 0x3f
126 beqz t1, .Lmemset_partial\@ /* no block to fill */
129 PTR_ADDU t1, a0 /* end address */
134 bne t1, a0, 1b
139 PTR_LA t1, 2f /* where to start */
144 PTR_SUBU t1, FILLPTRG
148 PTR_SUBU t1, AT
151 jr t1
176 PTR_ADDU t1, a
[all...]
/arch/x86/boot/
H A Dtty.c122 int t0, t1; local
130 t1 = gettime();
131 if (t0 != t1) {
133 t0 = t1;

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