Searched refs:DSPFW1 (Results 1 - 8 of 8) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| H A D | psb_device.c | 189 regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
227 PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
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| H A D | cdv_device.c | 278 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
348 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
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| H A D | oaktrail_device.c | 199 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
313 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
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| H A D | cdv_intel_display.c | 507 fw = REG_READ(DSPFW1);
512 REG_WRITE(DSPFW1, fw);
549 REG_WRITE(DSPFW1, 0x3f880808);
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| H A D | oaktrail_crtc.c | 337 REG_WRITE(DSPFW1, 0x3f8f0404);
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| H A D | psb_intel_reg.h | 614 #define DSPFW1 0x70034 macro
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| /drivers/gpu/drm/i915/ |
| H A D | intel_pm.c | 1132 reg = I915_READ(DSPFW1);
1135 I915_WRITE(DSPFW1, reg);
1136 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1436 I915_WRITE(DSPFW1,
1510 I915_WRITE(DSPFW1,
1603 I915_WRITE(DSPFW1,
1680 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
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| H A D | i915_reg.h | 3896 #define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034) macro
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