Searched refs:_MASKED_BIT_ENABLE (Results 1 - 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/
H A Dintel_ringbuffer.c496 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
718 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
723 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
726 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS));
733 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT));
737 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE));
778 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE));
782 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE));
786 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
790 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DI
[all...]
H A Dintel_pm.c846 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
850 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
4305 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4409 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5399 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
5470 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5515 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
5523 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
5616 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE));
5619 _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPT
[all...]
H A Dintel_lrc.c750 I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING));
1004 _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1029 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
1035 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
1538 _MASKED_BIT_ENABLE((1<<3) | MI_RESTORE_INHIBIT);
H A Dintel_uncore.c114 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
206 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
224 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
H A Di915_gem_gtt.c782 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
808 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
827 I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE));
H A Di915_gem.c4661 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB));
4663 I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB));
4665 I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW));
5027 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
H A Di915_reg.h35 #define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a)) macro

Completed in 126 milliseconds