/drivers/edac/ |
H A D | tile_edac.c | 128 struct edac_mc_layer layers[2]; local 138 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 139 layers[0].size = TILE_EDAC_NR_CSROWS; 140 layers[0].is_virt_csrow = true; 141 layers[1].type = EDAC_MC_LAYER_CHANNEL; 142 layers[1].size = TILE_EDAC_NR_CHANS; 143 layers[1].is_virt_csrow = false; 144 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
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H A D | amd76x_edac.c | 239 struct edac_mc_layer layers[2]; local 248 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 249 layers[0].size = AMD76X_NR_CSROWS; 250 layers[0].is_virt_csrow = true; 251 layers[1].type = EDAC_MC_LAYER_CHANNEL; 252 layers[1].size = 1; 253 layers[1].is_virt_csrow = false; 254 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
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H A D | highbank_mc_edac.c | 153 struct edac_mc_layer layers[2]; local 167 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 168 layers[0].size = 1; 169 layers[0].is_virt_csrow = true; 170 layers[1].type = EDAC_MC_LAYER_CHANNEL; 171 layers[1].size = 1; 172 layers[1].is_virt_csrow = false; 173 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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H A D | i82860_edac.c | 189 struct edac_mc_layer layers[2]; local 202 layers[0].type = EDAC_MC_LAYER_CHANNEL; 203 layers[0].size = 2; 204 layers[0].is_virt_csrow = true; 205 layers[1].type = EDAC_MC_LAYER_SLOT; 206 layers[1].size = 8; 207 layers[1].is_virt_csrow = true; 208 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
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H A D | pasemi_edac.c | 195 struct edac_mc_layer layers[2]; local 212 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 213 layers[0].size = PASEMI_EDAC_NR_CSROWS; 214 layers[0].is_virt_csrow = true; 215 layers[1].type = EDAC_MC_LAYER_CHANNEL; 216 layers[1].size = PASEMI_EDAC_NR_CHANS; 217 layers[1].is_virt_csrow = false; 218 mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers,
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H A D | r82600_edac.c | 273 struct edac_mc_layer layers[2]; local 287 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 288 layers[0].size = R82600_NR_CSROWS; 289 layers[0].is_virt_csrow = true; 290 layers[1].type = EDAC_MC_LAYER_CHANNEL; 291 layers[1].size = R82600_NR_CHANS; 292 layers[1].is_virt_csrow = false; 293 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
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H A D | altera_edac.c | 256 struct edac_mc_layer layers[2]; local 304 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 305 layers[0].size = 1; 306 layers[0].is_virt_csrow = true; 307 layers[1].type = EDAC_MC_LAYER_CHANNEL; 308 layers[1].size = 1; 309 layers[1].is_virt_csrow = false; 310 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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H A D | cell_edac.c | 172 struct edac_mc_layer layers[2]; local 202 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 203 layers[0].size = 1; 204 layers[0].is_virt_csrow = true; 205 layers[1].type = EDAC_MC_LAYER_CHANNEL; 206 layers[1].size = num_chans; 207 layers[1].is_virt_csrow = false; 208 mci = edac_mc_alloc(pdev->id, ARRAY_SIZE(layers), layers,
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H A D | i3000_edac.c | 316 struct edac_mc_layer layers[2]; local 359 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 360 layers[0].size = I3000_RANKS / nr_channels; 361 layers[0].is_virt_csrow = true; 362 layers[1].type = EDAC_MC_LAYER_CHANNEL; 363 layers[1].size = nr_channels; 364 layers[1].is_virt_csrow = false; 365 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
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H A D | i82443bxgx_edac.c | 237 struct edac_mc_layer layers[2]; local 251 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 252 layers[0].size = I82443BXGX_NR_CSROWS; 253 layers[0].is_virt_csrow = true; 254 layers[1].type = EDAC_MC_LAYER_CHANNEL; 255 layers[1].size = I82443BXGX_NR_CHANS; 256 layers[1].is_virt_csrow = false; 257 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
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H A D | x38_edac.c | 325 struct edac_mc_layer layers[2]; local 341 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 342 layers[0].size = X38_RANKS; 343 layers[0].is_virt_csrow = true; 344 layers[1].type = EDAC_MC_LAYER_CHANNEL; 345 layers[1].size = x38_channel_num; 346 layers[1].is_virt_csrow = false; 347 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
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H A D | ie31200_edac.c | 333 struct edac_mc_layer layers[2]; local 347 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 348 layers[0].size = IE31200_DIMMS; 349 layers[0].is_virt_csrow = true; 350 layers[1].type = EDAC_MC_LAYER_CHANNEL; 351 layers[1].size = nr_channels; 352 layers[1].is_virt_csrow = false; 353 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 414 dimm = EDAC_DIMM_PTR(mci->layers, mc [all...] |
H A D | octeon_edac-lmc.c | 245 struct edac_mc_layer layers[1]; local 250 layers[0].type = EDAC_MC_LAYER_CHANNEL; 251 layers[0].size = 1; 252 layers[0].is_virt_csrow = false; 263 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt)); 301 mci = edac_mc_alloc(mc, ARRAY_SIZE(layers), layers, sizeof(struct octeon_lmc_pvt));
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H A D | i3200_edac.c | 343 struct edac_mc_layer layers[2]; local 358 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 359 layers[0].size = I3200_DIMMS; 360 layers[0].is_virt_csrow = true; 361 layers[1].type = EDAC_MC_LAYER_CHANNEL; 362 layers[1].size = nr_channels; 363 layers[1].is_virt_csrow = false; 364 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 398 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mc [all...] |
H A D | e7xxx_edac.c | 426 struct edac_mc_layer layers[2]; local 445 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 446 layers[0].size = E7XXX_NR_CSROWS; 447 layers[0].is_virt_csrow = true; 448 layers[1].type = EDAC_MC_LAYER_CHANNEL; 449 layers[1].size = drc_chan + 1; 450 layers[1].is_virt_csrow = false; 451 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
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H A D | i82875p_edac.c | 393 struct edac_mc_layer layers[2]; local 408 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 409 layers[0].size = I82875P_NR_CSROWS(nr_chans); 410 layers[0].is_virt_csrow = true; 411 layers[1].type = EDAC_MC_LAYER_CHANNEL; 412 layers[1].size = nr_chans; 413 layers[1].is_virt_csrow = false; 414 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
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H A D | i82975x_edac.c | 476 struct edac_mc_layer layers[2]; local 545 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 546 layers[0].size = I82975X_NR_DIMMS; 547 layers[0].is_virt_csrow = true; 548 layers[1].type = EDAC_MC_LAYER_CHANNEL; 549 layers[1].size = I82975X_NR_CSROWS(chans); 550 layers[1].is_virt_csrow = false; 551 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
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H A D | edac_mc.c | 59 edac_layer_name[mci->layers[i].type], 240 * @n_layers: Number of MC hierarchy layers 241 * layers: Describes each layer as seen by the Memory Controller 263 struct edac_mc_layer *layers, 285 tot_dimms *= layers[i].size; 286 if (layers[i].is_virt_csrow) 287 tot_csrows *= layers[i].size; 289 tot_channels *= layers[i].size; 291 if (layers[i].type == EDAC_MC_LAYER_CHIP_SELECT) 303 count *= layers[ 261 edac_mc_alloc(unsigned mc_num, unsigned n_layers, struct edac_mc_layer *layers, unsigned sz_pvt) argument [all...] |
H A D | ghes_edac.c | 104 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, 433 struct edac_mc_layer layers[1]; local 446 layers[0].type = EDAC_MC_LAYER_ALL_MEM; 447 layers[0].size = num_dimm; 448 layers[0].is_virt_csrow = true; 455 mci = edac_mc_alloc(ghes_edac_mc_num, ARRAY_SIZE(layers), layers, 509 struct dimm_info *dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms,
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H A D | i5400_edac.c | 1188 * layers here. 1190 for (channel = 0; channel < mci->layers[0].size * mci->layers[1].size; 1192 for (slot = 0; slot < mci->layers[2].size; slot++) { 1199 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 1265 struct edac_mc_layer layers[3]; local 1283 layers[0].type = EDAC_MC_LAYER_BRANCH; 1284 layers[0].size = MAX_BRANCHES; 1285 layers[0].is_virt_csrow = false; 1286 layers[ [all...] |
H A D | ppc4xx_edac.c | 1237 struct edac_mc_layer layers[2]; local 1283 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; 1284 layers[0].size = ppc4xx_edac_nr_csrows; 1285 layers[0].is_virt_csrow = true; 1286 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1287 layers[1].size = ppc4xx_edac_nr_chans; 1288 layers[1].is_virt_csrow = false; 1289 mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
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H A D | i5000_edac.c | 1285 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, 1365 struct edac_mc_layer layers[3]; local 1399 layers[0].type = EDAC_MC_LAYER_BRANCH; 1400 layers[0].size = MAX_BRANCHES; 1401 layers[0].is_virt_csrow = false; 1402 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1403 layers[1].size = num_channels / MAX_BRANCHES; 1404 layers[1].is_virt_csrow = false; 1405 layers[2].type = EDAC_MC_LAYER_SLOT; 1406 layers[ [all...] |
H A D | i7300_edac.c | 799 dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, 1027 struct edac_mc_layer layers[3]; local 1045 layers[0].type = EDAC_MC_LAYER_BRANCH; 1046 layers[0].size = MAX_BRANCHES; 1047 layers[0].is_virt_csrow = false; 1048 layers[1].type = EDAC_MC_LAYER_CHANNEL; 1049 layers[1].size = MAX_CH_PER_BRANCH; 1050 layers[1].is_virt_csrow = true; 1051 layers[2].type = EDAC_MC_LAYER_SLOT; 1052 layers[ [all...] |
/drivers/media/dvb-frontends/ |
H A D | tc90522.c | 210 int layers; local 218 layers = 0; 242 layers = (v > 0) ? 2 : 1; 290 stats->len = layers; 293 for (i = 0; i < layers; i++) 296 for (i = 0; i < layers; i++) { 304 stats->len = layers; 306 for (i = 0; i < layers; i++) 309 for (i = 0; i < layers; i++) { 342 int layers; local [all...] |
/drivers/parisc/ |
H A D | pdc_stable.c | 372 for (i = 0; i < 6 && devpath->layers[i]; i++) 373 out += sprintf(out, "%u ", devpath->layers[i]); 395 unsigned int layers[6]; /* device-specific info (ctlr#, unit#, ...) */ local 408 memset(&layers, 0, sizeof(layers)); 413 layers[0] = simple_strtoul(in, NULL, 10); 414 DPRINTK("%s: layer[0]: %d\n", __func__, layers[0]); 420 layers[i] = simple_strtoul(temp, NULL, 10); 421 DPRINTK("%s: layer[%d]: %d\n", __func__, i, layers[i]); 427 /* First, overwrite the current layers wit [all...] |