/drivers/net/ethernet/stmicro/stmmac/ |
H A D | stmmac_hwtstamp.c | 56 int limit; local 67 limit = 10; 68 while (limit--) { 73 if (limit < 0) 82 int limit; local 91 limit = 10; 92 while (limit--) { 97 if (limit < 0) 107 int limit; local 118 limit [all...] |
H A D | dwmac1000_dma.c | 37 int limit; local 42 limit = 10; 43 while (limit--) { 48 if (limit < 0)
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H A D | dwmac100_dma.c | 39 int limit; local 44 limit = 10; 45 while (limit--) { 50 if (limit < 0)
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/drivers/gpu/drm/radeon/ |
H A D | kv_smc.c | 76 u32 smc_address, u32 limit) 80 if ((smc_address + 3) > limit) 90 u32 *value, u32 limit) 94 ret = kv_set_smc_sram_address(rdev, smc_address, limit); 120 const u8 *src, u32 byte_count, u32 limit) 125 if ((smc_start_address + byte_count) > limit) 135 ret = kv_set_smc_sram_address(rdev, addr, limit); 161 ret = kv_set_smc_sram_address(rdev, addr, limit); 174 ret = kv_set_smc_sram_address(rdev, addr, limit); 189 ret = kv_set_smc_sram_address(rdev, addr, limit); 75 kv_set_smc_sram_address(struct radeon_device *rdev, u32 smc_address, u32 limit) argument 89 kv_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, u32 *value, u32 limit) argument 118 kv_copy_bytes_to_smc(struct radeon_device *rdev, u32 smc_start_address, const u8 *src, u32 byte_count, u32 limit) argument [all...] |
H A D | ci_smc.c | 34 u32 smc_address, u32 limit) 38 if ((smc_address + 3) > limit) 49 const u8 *src, u32 byte_count, u32 limit) 59 if ((smc_start_address + byte_count) > limit) 69 ret = ci_set_smc_sram_address(rdev, addr, limit); 84 ret = ci_set_smc_sram_address(rdev, addr, limit); 101 ret = ci_set_smc_sram_address(rdev, addr, limit); 205 int ci_load_smc_ucode(struct radeon_device *rdev, u32 limit) argument 266 u32 smc_address, u32 *value, u32 limit) 272 ret = ci_set_smc_sram_address(rdev, smc_address, limit); 33 ci_set_smc_sram_address(struct radeon_device *rdev, u32 smc_address, u32 limit) argument 47 ci_copy_bytes_to_smc(struct radeon_device *rdev, u32 smc_start_address, const u8 *src, u32 byte_count, u32 limit) argument 265 ci_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, u32 *value, u32 limit) argument 280 ci_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, u32 value, u32 limit) argument [all...] |
H A D | si_smc.c | 34 u32 smc_address, u32 limit) 38 if ((smc_address + 3) > limit) 49 const u8 *src, u32 byte_count, u32 limit) 57 if ((smc_start_address + byte_count) > limit) 67 ret = si_set_smc_sram_address(rdev, addr, limit); 82 ret = si_set_smc_sram_address(rdev, addr, limit); 100 ret = si_set_smc_sram_address(rdev, addr, limit); 211 int si_load_smc_ucode(struct radeon_device *rdev, u32 limit) argument 283 u32 *value, u32 limit) 289 ret = si_set_smc_sram_address(rdev, smc_address, limit); 33 si_set_smc_sram_address(struct radeon_device *rdev, u32 smc_address, u32 limit) argument 47 si_copy_bytes_to_smc(struct radeon_device *rdev, u32 smc_start_address, const u8 *src, u32 byte_count, u32 limit) argument 282 si_read_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, u32 *value, u32 limit) argument 297 si_write_smc_sram_dword(struct radeon_device *rdev, u32 smc_address, u32 value, u32 limit) argument [all...] |
/drivers/usb/host/ |
H A D | xhci-ext-caps.h | 138 * This uses an arbitrary limit of XHCI_MAX_EXT_CAPS extended capabilities 144 int limit = XHCI_MAX_EXT_CAPS; local 146 while (ext_offset && limit > 0) { 151 limit--; 153 if (limit > 0)
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/drivers/clk/bcm/ |
H A D | clk-kona-setup.c | 31 u32 limit; local 33 limit = ccu->range - sizeof(u32); 34 limit = round_down(limit, sizeof(u32)); 36 if (ccu_policy->enable.offset > limit) { 39 ccu->name, ccu_policy->enable.offset, limit); 42 if (ccu_policy->control.offset > limit) { 45 ccu->name, ccu_policy->control.offset, limit); 90 u32 limit; local 97 limit 184 u32 limit = BITS_PER_BYTE * sizeof(u32) - 1; local 204 u32 limit = BITS_PER_BYTE * sizeof(u32); local 301 u32 limit; local 375 u32 limit; local [all...] |
/drivers/gpu/drm/nouveau/ |
H A D | nv50_fence.c | 42 u32 limit = start + mem->size - 1; local 59 .limit = limit, 67 u32 limit = start + bo->bo.mem.size - 1; local 74 .limit = limit,
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H A D | nouveau_chan.c | 139 args.limit = cli->vm->vmm->limit - 1; 150 args.limit = args.start + device->info.ram_user - 1; 155 args.limit = device->info.ram_user - 1; 162 args.limit = chan->drm->agp.base + 168 args.limit = vmm->limit - 1; 298 args.limit = cli->vm->vmm->limit - 1; 303 args.limit [all...] |
/drivers/gpu/drm/nouveau/core/include/engine/ |
H A D | dmaobj.h | 14 u64 limit; member in struct:nouveau_dmaobj
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/drivers/gpu/drm/nouveau/core/subdev/fb/ |
H A D | nv10.c | 34 tile->limit = max(1u, addr + size) - 1; 42 tile->limit = 0; 50 nv_wr32(pfb, 0x100244 + (i * 0x10), tile->limit);
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H A D | nv44.c | 35 tile->limit = max(1u, addr + size) - 1; 42 nv_wr32(pfb, 0x100604 + (i * 0x10), tile->limit);
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/drivers/gpu/drm/gma500/ |
H A D | oaktrail_crtc.c | 46 static bool mrst_lvds_find_best_pll(const struct gma_limit_t *limit, 50 static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, 93 const struct gma_limit_t *limit = NULL; local 101 limit = &mrst_limits[MRST_LIMIT_LVDS_100L]; 104 limit = &mrst_limits[MRST_LIMIT_LVDS_83]; 107 limit = &mrst_limits[MRST_LIMIT_LVDS_100]; 111 limit = &mrst_limits[MRST_LIMIT_SDVO]; 113 limit = NULL; 117 return limit; 133 static bool mrst_sdvo_find_best_pll(const struct gma_limit_t *limit, argument 190 mrst_lvds_find_best_pll(const struct gma_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, struct gma_clock_t *best_clock) argument 377 const struct gma_limit_t *limit; local [all...] |
H A D | gma_display.h | 58 const struct gma_limit_t *(*limit)(struct drm_crtc *crtc, int refclk); member in struct:gma_clock_funcs 60 const struct gma_limit_t *limit, 101 const struct gma_limit_t *limit, 103 extern bool gma_find_best_pll(const struct gma_limit_t *limit,
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H A D | gma_display.c | 700 const struct gma_limit_t *limit, 703 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 705 if (clock->p < limit->p.min || limit->p.max < clock->p) 707 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 709 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 714 if (clock->m < limit 699 gma_pll_is_valid(struct drm_crtc *crtc, const struct gma_limit_t *limit, struct gma_clock_t *clock) argument 730 gma_find_best_pll(const struct gma_limit_t *limit, struct drm_crtc *crtc, int target, int refclk, struct gma_clock_t *best_clock) argument [all...] |
/drivers/net/wireless/ath/ath9k/ |
H A D | calib.c | 50 struct ath_nf_limits *limit; local 53 limit = &ah->nf_2g; 55 limit = &ah->nf_5g; 57 return limit; 86 struct ath_nf_limits *limit; local 93 limit = ath9k_hw_get_nf_limits(ah, ah->curchan); 116 if (h[i].privNF > limit->max) { 121 i, h[i].privNF, limit->max, 127 * Normally we limit the average noise floor by the 130 * we bypass this limit her 331 struct ath_nf_limits *limit; local [all...] |
/drivers/base/ |
H A D | dma-contiguous.c | 100 * @limit: End address of the reserved memory (optional, 0 for any). 107 void __init dma_contiguous_reserve(phys_addr_t limit) argument 111 phys_addr_t selected_limit = limit; 114 pr_debug("%s(limit %08lx)\n", __func__, (unsigned long)limit); 119 selected_limit = min_not_zero(limit_cmdline, limit); 149 * @limit: End address of the reserved memory (optional, 0 for any). 160 * reserve in range from @base to @limit. 163 phys_addr_t limit, struct cma **res_cma, 168 ret = cma_declare_contiguous(base, size, limit, 162 dma_contiguous_reserve_area(phys_addr_t size, phys_addr_t base, phys_addr_t limit, struct cma **res_cma, bool fixed) argument [all...] |
/drivers/scsi/be2iscsi/ |
H A D | be.h | 48 static inline u32 MODULO(u16 val, u16 limit) argument 50 WARN_ON(limit & (limit - 1)); 51 return val & (limit - 1); 54 static inline void index_inc(u16 *index, u16 limit) argument 56 *index = MODULO((*index + 1), limit);
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/drivers/net/wireless/iwlwifi/ |
H A D | iwl-debug.c | 116 u32 level, bool limit, const char *function, 128 (!limit || net_ratelimit())) 115 __iwl_dbg(struct device *dev, u32 level, bool limit, const char *function, const char *fmt, ...) argument
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/drivers/gpu/drm/nouveau/core/engine/dmaobj/ |
H A D | base.c | 83 "start %016llx limit %016llx\n", 85 args->v0.start, args->v0.limit); 89 dmaobj->limit = args->v0.limit; 96 if (dmaobj->start > dmaobj->limit) 105 if (dmaobj->limit >= pfb->ram->size - instmem->reserved)
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/drivers/infiniband/hw/qib/ |
H A D | qib_diag.c | 258 /* If user regs mapped, they are after send, so set limit. */ 286 * appropriate limit. 342 u32 limit; local 345 reg_addr = (const u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); 346 if (reg_addr == NULL || limit == 0 || !(dd->flags & QIB_PRESENT)) { 350 if (count >= limit) 351 count = limit; 386 u32 limit; local 389 reg_addr = (u64 __iomem *)qib_remap_ioaddr32(dd, regoffs, &limit); 390 if (reg_addr == NULL || limit 430 u32 limit; local 476 u32 limit; local [all...] |
/drivers/staging/speakup/ |
H A D | selection.c | 47 static unsigned short limit(const unsigned short v, const unsigned short u) function 59 spk_xs = limit(spk_xs, vc->vc_cols - 1); 60 spk_ys = limit(spk_ys, vc->vc_rows - 1); 61 spk_xe = limit(spk_xe, vc->vc_cols - 1); 62 spk_ye = limit(spk_ye, vc->vc_rows - 1);
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/drivers/gpu/drm/nouveau/core/subdev/bar/ |
H A D | nv50.c | 115 u64 start, limit; local 142 limit = start + nv_device_resource_len(device, 3); 144 ret = nouveau_vm_new(device, start, limit, start, &vm); 151 ((limit-- - start) >> 12) * 8, 0x1000, 167 nv_wo32(priv->bar3, 0x04, lower_32_bits(limit)); 169 nv_wo32(priv->bar3, 0x0c, upper_32_bits(limit) << 24 | 176 limit = start + nv_device_resource_len(device, 1); 178 ret = nouveau_vm_new(device, start, limit--, start, &vm); 194 nv_wo32(priv->bar1, 0x04, lower_32_bits(limit)); 196 nv_wo32(priv->bar1, 0x0c, upper_32_bits(limit) << 2 [all...] |
/drivers/tty/serial/ |
H A D | sunhv.c | 78 int limit = 10000; local 80 while (limit-- > 0) { 121 int limit = 10000; local 123 while (limit-- > 0) { 269 int limit = 10000; local 276 while (limit-- > 0) { 296 int limit = 10000; local 300 while (limit-- > 0) { 448 int limit = 1000000; local 450 while (limit 472 int limit = 1000000; local [all...] |