Searched refs:parent_name (Results 1 - 25 of 92) sorted by relevance

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/drivers/clk/berlin/
H A Dcommon.h24 const char *parent_name; member in struct:berlin2_gate_data
H A Dberlin2-avpll.h29 const char *parent_name, u8 vco_flags, unsigned long flags);
33 u8 index, const char *parent_name, u8 ch_flags,
H A Dberlin2-pll.h35 const char *parent_name, unsigned long flags);
/drivers/clk/ux500/
H A Dclk.h18 const char *parent_name,
24 const char *parent_name,
30 const char *parent_name,
36 const char *parent_name,
41 const char *parent_name,
47 const char *parent_name,
52 const char *parent_name,
57 const char *parent_name,
64 const char *parent_name,
73 const char *parent_name,
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H A Dclk-prcc.c96 const char *parent_name,
127 clk_prcc_init.parent_names = (parent_name ? &parent_name : NULL);
128 clk_prcc_init.num_parents = (parent_name ? 1 : 0);
146 const char *parent_name,
151 return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
156 const char *parent_name,
161 return clk_reg_prcc(name, parent_name, phy_base, cg_sel, flags,
95 clk_reg_prcc(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags, struct clk_ops *clk_prcc_ops) argument
145 clk_reg_prcc_pclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags) argument
155 clk_reg_prcc_kclk(const char *name, const char *parent_name, resource_size_t phy_base, u32 cg_sel, unsigned long flags) argument
H A Dclk-prcmu.c247 const char *parent_name,
279 clk_prcmu_init.parent_names = (parent_name ? &parent_name : NULL);
280 clk_prcmu_init.num_parents = (parent_name ? 1 : 0);
296 const char *parent_name,
301 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
306 const char *parent_name,
310 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
315 const char *parent_name,
320 return clk_reg_prcmu(name, parent_name, cg_se
246 clk_reg_prcmu(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags, struct clk_ops *clk_prcmu_ops) argument
295 clk_reg_prcmu_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) argument
305 clk_reg_prcmu_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) argument
314 clk_reg_prcmu_scalable_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) argument
324 clk_reg_prcmu_rate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) argument
333 clk_reg_prcmu_opp_gate(const char *name, const char *parent_name, u8 cg_sel, unsigned long flags) argument
342 clk_reg_prcmu_opp_volt_scalable(const char *name, const char *parent_name, u8 cg_sel, unsigned long rate, unsigned long flags) argument
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/drivers/clk/mxs/
H A Dclk.h26 struct clk *mxs_clk_pll(const char *name, const char *parent_name,
29 struct clk *mxs_clk_ref(const char *name, const char *parent_name,
32 struct clk *mxs_clk_div(const char *name, const char *parent_name,
35 struct clk *mxs_clk_frac(const char *name, const char *parent_name,
44 const char *parent_name, void __iomem *reg, u8 shift)
46 return clk_register_gate(NULL, name, parent_name, CLK_SET_RATE_PARENT,
60 const char *parent_name, unsigned int mult, unsigned int div)
62 return clk_register_fixed_factor(NULL, name, parent_name,
43 mxs_clk_gate(const char *name, const char *parent_name, void __iomem *reg, u8 shift) argument
59 mxs_clk_fixed_factor(const char *name, const char *parent_name, unsigned int mult, unsigned int div) argument
H A Dclk-pll.c89 struct clk *mxs_clk_pll(const char *name, const char *parent_name, argument
103 init.parent_names = (parent_name ? &parent_name: NULL);
104 init.num_parents = (parent_name ? 1 : 0);
/drivers/clk/mmp/
H A Dclk.h24 const char *parent_name, unsigned long flags);
26 const char *parent_name, void __iomem *base,
29 const char *parent_name, void __iomem *base, u32 enable_mask,
32 const char *parent_name, unsigned long flags,
H A Dclk-apmu.c69 struct clk *mmp_clk_register_apmu(const char *name, const char *parent_name, argument
83 init.parent_names = (parent_name ? &parent_name : NULL);
84 init.num_parents = (parent_name ? 1 : 0);
/drivers/clk/versatile/
H A Dclk-icst.h19 const char *parent_name,
/drivers/clk/shmobile/
H A Dclk-r8a7740.c69 const char *parent_name; local
78 parent_name = of_clk_get_parent_name(np, 0);
83 parent_name = of_clk_get_parent_name(np, 0);
88 parent_name = of_clk_get_parent_name(np, 2);
92 parent_name = of_clk_get_parent_name(np, 0);
102 parent_name = "system";
106 parent_name = "system";
111 parent_name = "system";
117 parent_name = of_clk_get_parent_name(np, 1);
119 parent_name
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H A Dclk-rcar-gen2.c138 static const char *parent_name = "pll0"; local
150 init.parent_names = &parent_name;
222 const char *parent_name; local
228 parent_name = of_clk_get_parent_name(np, 0);
237 parent_name = "main";
240 parent_name = "main";
243 parent_name = "main";
246 parent_name = "pll1";
249 parent_name = "pll1_div2";
253 parent_name
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H A Dclk-emev2.c75 const char *parent_name = of_clk_get_parent_name(np, 0); local
80 clk = clk_register_divider(NULL, np->name, parent_name, 0,
93 const char *parent_name = of_clk_get_parent_name(np, 0); local
98 clk = clk_register_gate(NULL, np->name, parent_name, 0,
/drivers/clk/ti/
H A Dfixed-factor.c38 const char *parent_name; local
55 parent_name = of_clk_get_parent_name(node, 0);
57 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, flags,
/drivers/clk/
H A Dclk-moxart.c24 const char *parent_name; local
27 parent_name = of_clk_get_parent_name(node, 0);
44 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mul, 1);
63 const char *parent_name; local
66 parent_name = of_clk_get_parent_name(node, 0);
87 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, 1, div);
H A Dclk-fixed-rate.c54 * @parent_name: name of clock's parent
60 const char *name, const char *parent_name, unsigned long flags,
77 init.parent_names = (parent_name ? &parent_name: NULL);
78 init.num_parents = (parent_name ? 1 : 0);
98 * @parent_name: name of clock's parent
103 const char *parent_name, unsigned long flags,
106 return clk_register_fixed_rate_with_accuracy(dev, name, parent_name,
59 clk_register_fixed_rate_with_accuracy(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate, unsigned long fixed_accuracy) argument
102 clk_register_fixed_rate(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned long fixed_rate) argument
H A Dclk-fixed-factor.c69 const char *parent_name, unsigned long flags,
90 init.parent_names = &parent_name;
110 const char *parent_name; local
126 parent_name = of_clk_get_parent_name(node, 0);
128 clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
68 clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) argument
/drivers/clk/hisilicon/
H A Dclk.h41 const char *parent_name; member in struct:hisi_fixed_rate_clock
49 const char *parent_name; member in struct:hisi_fixed_factor_clock
72 const char *parent_name; member in struct:hisi_divider_clock
85 const char *parent_name; member in struct:hisi_gate_clock
/drivers/clk/at91/
H A Dclk-plldiv.c84 const char *parent_name)
96 init.parent_names = parent_name ? &parent_name : NULL;
97 init.num_parents = parent_name ? 1 : 0;
115 const char *parent_name; local
118 parent_name = of_clk_get_parent_name(np, 0);
122 clk = at91_clk_register_plldiv(pmc, name, parent_name);
83 at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name, const char *parent_name) argument
H A Dclk-peripheral.c105 const char *parent_name, u32 id)
111 if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX)
120 init.parent_names = (parent_name ? &parent_name : NULL);
121 init.num_parents = (parent_name ? 1 : 0);
314 const char *parent_name, u32 id,
321 if (!pmc || !name || !parent_name)
330 init.parent_names = (parent_name ? &parent_name : NULL);
331 init.num_parents = (parent_name
104 at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id) argument
313 at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name, const char *parent_name, u32 id, const struct clk_range *range) argument
356 const char *parent_name; local
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H A Dclk-h32mx.c100 const char *parent_name; local
107 parent_name = of_clk_get_parent_name(np, 0);
111 init.parent_names = parent_name ? &parent_name : NULL;
112 init.num_parents = parent_name ? 1 : 0;
H A Dclk-utmi.c97 const char *name, const char *parent_name)
110 init.parent_names = parent_name ? &parent_name : NULL;
111 init.num_parents = parent_name ? 1 : 0;
136 const char *parent_name; local
139 parent_name = of_clk_get_parent_name(np, 0);
147 clk = at91_clk_register_utmi(pmc, irq, name, parent_name);
96 at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq, const char *name, const char *parent_name) argument
/drivers/clk/socfpga/
H A Dclk.h44 char *parent_name; member in struct:socfpga_gate_clk
54 char *parent_name; member in struct:socfpga_periph_clk
/drivers/clk/keystone/
H A Dpll.c121 const char *parent_name,
135 init.parent_names = (parent_name ? &parent_name : NULL);
136 init.num_parents = (parent_name ? 1 : 0);
160 const char *parent_name; local
170 parent_name = of_clk_get_parent_name(node, 0);
200 clk = clk_register_pll(NULL, node->name, parent_name, pll_data);
239 const char *parent_name; local
252 parent_name = of_clk_get_parent_name(node, 0);
253 if (!parent_name) {
119 clk_register_pll(struct device *dev, const char *name, const char *parent_name, struct clk_pll_data *pll_data) argument
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