/drivers/gpu/drm/gma500/ |
H A D | mdfld_dsi_dpi.c | 134 REG_WRITE(pipeconf_reg, BIT(31)); 141 REG_WRITE(dspcntr_reg, dspcntr); 157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); 243 REG_WRITE(gen_data_reg, 0x00008036); 245 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); 249 REG_WRITE(gen_data_reg, 0x005a5af0); 251 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); 255 REG_WRITE(gen_data_reg, 0x005a5af1); 257 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); 261 REG_WRITE(gen_data_re [all...] |
H A D | mdfld_intel_display.c | 143 REG_WRITE(dspcntr_reg, dspcntr); 201 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); 220 REG_WRITE(map->cntr, dspcntr); 224 REG_WRITE(map->linoff, offset); 226 REG_WRITE(map->surf, start); 254 REG_WRITE(map->cntr, 257 REG_WRITE(map->base, REG_READ(map->base)); 268 REG_WRITE(map->conf, temp); 281 REG_WRITE(map->dpll, temp); 289 REG_WRITE(ma [all...] |
H A D | cdv_device.c | 46 REG_WRITE(vga_reg, VGA_DISP_DISABLE); 146 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl | 327 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D); 328 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D); 331 REG_WRITE(DPIO_CFG, 0); 332 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 336 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE); 342 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE); 348 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]); 349 REG_WRITE(DSPFW [all...] |
H A D | oaktrail_hdmi.c | 288 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); 293 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET)); 294 REG_WRITE(DPLL_DIV_CTRL, 0x00000000); 295 REG_WRITE(DPLL_STATUS, 0x1); 310 REG_WRITE(DPLL_CTRL, 0x00000008); 311 REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr)); 312 REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1)); 313 REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN)); 314 REG_WRITE(DPLL_UPDATE, 0x80000000); 315 REG_WRITE(DPLL_CLK_ENABL [all...] |
H A D | gma_display.c | 86 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]); 110 REG_WRITE(map->cntr, dspcntr); 119 REG_WRITE(map->base, offset + start); 122 REG_WRITE(map->base, offset); 124 REG_WRITE(map->surf, start); 154 REG_WRITE(palreg + 4 * i, 228 REG_WRITE(map->dpll, temp); 232 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 236 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); 245 REG_WRITE(ma [all...] |
H A D | cdv_intel_display.c | 149 REG_WRITE(SB_ADDR, reg); 150 REG_WRITE(SB_PCKT, 184 REG_WRITE(SB_ADDR, reg); 185 REG_WRITE(SB_DATA, val); 186 REG_WRITE(SB_PCKT, 211 REG_WRITE(DPIO_CFG, 0); 213 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N); 236 REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS); 482 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN)); 490 REG_WRITE(OV_OVAD [all...] |
H A D | psb_lid.c | 40 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) | POWER_TARGET_ON); 56 REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) & ~POWER_TARGET_ON);
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/drivers/net/wireless/ath/ |
H A D | hw.c | 24 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro 123 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr)); 126 REG_WRITE(ah, AR_STA_ID1, id1); 128 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask)); 129 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4)); 148 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 157 REG_WRITE(ah, AR_CCCNT, 0); 158 REG_WRITE(ah, AR_RFCNT, 0); 159 REG_WRITE(ah, AR_RCCNT, 0); 160 REG_WRITE(a [all...] |
H A D | key.c | 26 #define REG_WRITE(_ah, _reg, _val) (common->ops->write)(_ah, _val, _reg) macro 57 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0); 58 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0); 59 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0); 60 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0); 61 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0); 62 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR); 63 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0); 64 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0); 69 REG_WRITE(a [all...] |
/drivers/net/dsa/ |
H A D | mv88e6171.c | 46 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); 53 REG_WRITE(REG_GLOBAL, 0x04, 0xc400); 73 REG_WRITE(REG_PORT(i), 0x04, ret | 0x03); 88 REG_WRITE(REG_GLOBAL, 0x04, 0x0000); 94 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); 106 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1111)); 108 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); 113 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); 118 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); 123 REG_WRITE(REG_GLOBAL [all...] |
H A D | mv88e6123_61_65.c | 64 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); 71 REG_WRITE(REG_GLOBAL, 0x04, 0xc400); 97 REG_WRITE(REG_GLOBAL, 0x04, 0x0000); 103 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); 114 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1110)); 119 REG_WRITE(REG_GLOBAL, 0x1c, ds->index & 0x1f); 124 REG_WRITE(REG_GLOBAL2, 0x02, 0xffff); 129 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); 138 REG_WRITE(REG_GLOBAL2, 0x05, 0x00ff); 148 REG_WRITE(REG_GLOBAL [all...] |
H A D | mv88e6131.c | 56 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); 63 REG_WRITE(REG_GLOBAL, 0x04, 0xc400); 90 REG_WRITE(REG_GLOBAL, 0x04, 0x4400); 96 REG_WRITE(REG_GLOBAL, 0x0a, 0x0148); 104 REG_WRITE(REG_GLOBAL, 0x19, 0x8100); 110 REG_WRITE(REG_GLOBAL, 0x1a, (dsa_upstream_port(ds) * 0x1100) | 0x00f0); 117 REG_WRITE(REG_GLOBAL, 0x1c, 0xf000 | (ds->index & 0x1f)); 119 REG_WRITE(REG_GLOBAL, 0x1c, 0xe000 | (ds->index & 0x1f)); 124 REG_WRITE(REG_GLOBAL2, 0x03, 0xffff); 131 REG_WRITE(REG_GLOBAL [all...] |
H A D | mv88e6060.c | 53 #define REG_WRITE(addr, reg, val) \ macro 89 REG_WRITE(REG_PORT(i), 0x04, ret & 0xfffc); 96 REG_WRITE(REG_GLOBAL, 0x0a, 0xa130); 119 REG_WRITE(REG_GLOBAL, 0x04, 0x0800); 125 REG_WRITE(REG_GLOBAL, 0x0a, 0x2130); 139 REG_WRITE(addr, 0x04, dsa_is_cpu_port(ds, p) ? 0x4103 : 0x0003); 146 REG_WRITE(addr, 0x06, 157 REG_WRITE(addr, 0x0b, 1 << p); 188 REG_WRITE(REG_GLOBAL, 0x01, (addr[0] << 8) | addr[1]); 189 REG_WRITE(REG_GLOBA [all...] |
H A D | mv88e6xxx.c | 141 REG_WRITE(REG_GLOBAL, 0x10, 0x0000); 142 REG_WRITE(REG_GLOBAL, 0x11, 0x0000); 143 REG_WRITE(REG_GLOBAL, 0x12, 0x5555); 144 REG_WRITE(REG_GLOBAL, 0x13, 0x5555); 145 REG_WRITE(REG_GLOBAL, 0x14, 0xaaaa); 146 REG_WRITE(REG_GLOBAL, 0x15, 0xaaaa); 147 REG_WRITE(REG_GLOBAL, 0x16, 0xffff); 148 REG_WRITE(REG_GLOBAL, 0x17, 0xffff); 151 REG_WRITE(REG_GLOBAL, 0x18, 0xfa41); 158 REG_WRITE(REG_GLOBA [all...] |
/drivers/media/usb/dvb-usb-v2/ |
H A D | ce6230.h | 47 REG_WRITE = 0xcf, /* wr f */ enumerator in enum:ce6230_cmd
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/drivers/net/wireless/ath/ath9k/ |
H A D | ar9002_phy.c | 101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 249 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal); 256 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal); 286 REG_WRITE(ah, AR_PHY_TIMING11, newVal); 289 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal); 307 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 308 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 341 REG_WRITE(a [all...] |
H A D | ar9003_wow.c | 44 REG_WRITE(ah, AR_CR, AR_CR_RXD); 52 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_ON_INT); 76 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); 78 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + i * 4), ctl[i]); 95 REG_WRITE(ah, (AR_WOW_KA_DESC_WORD2 + (12 * 4)), 0); 102 REG_WRITE(ah, (wow_ka_data_word0 + i*4), data_word[i]); 123 REG_WRITE(ah, (AR_WOW_TB_PATTERN(pattern_count) + i), 131 REG_WRITE(ah, (AR_WOW_TB_MASK(pattern_count) + i), mask_val); 218 REG_WRITE(ah, AR_WOW_PATTERN, 224 REG_WRITE(a [all...] |
H A D | hw.c | 116 REG_WRITE(ah, INI_RA(array, r, 0), 283 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 284 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 285 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029); 286 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824); 287 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579); 288 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000); 289 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 290 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 291 REG_WRITE(a [all...] |
H A D | ar9002_hw.c | 219 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0), 225 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00); 226 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924); 229 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039); 230 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824); 231 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579); 237 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff); 239 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40); 240 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554); 241 REG_WRITE(a [all...] |
H A D | ar5008_phy.c | 58 REG_WRITE(ah, INI_RA(array, r, 0), data[r]); 203 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 206 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, 235 REG_WRITE(ah, AR_PHY(0x37), reg32); 303 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new); 310 REG_WRITE(ah, AR_PHY_SPUR_REG, new); 321 REG_WRITE(ah, AR_PHY_TIMING11, new); 339 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask); 340 REG_WRITE(ah, chan_mask_reg[i], chan_mask); 373 REG_WRITE(a [all...] |
H A D | ar9003_mci.c | 47 REG_WRITE(ah, address, bit_position); 57 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 60 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, AR_MCI_INTERRUPT_RX_MSG); 233 REG_WRITE(ah, AR_MCI_INTERRUPT_EN, 0); 234 REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_RAW, 236 REG_WRITE(ah, AR_MCI_INTERRUPT_RAW, 271 REG_WRITE(ah, AR_MCI_BT_PRI0, 0xFFFFFFFF); 272 REG_WRITE(ah, AR_MCI_BT_PRI1, 0xFFFFFFFF); 273 REG_WRITE(ah, AR_MCI_BT_PRI2, 0xFFFFFFFF); 274 REG_WRITE(a [all...] |
H A D | mac.c | 32 REG_WRITE(ah, AR_IMR_S0, 35 REG_WRITE(ah, AR_IMR_S1, 41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg); 54 REG_WRITE(ah, AR_QTXDP(q), txdp); 61 REG_WRITE(ah, AR_Q_TXE, 1 << q); 123 REG_WRITE(ah, AR_TXCFG, 146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M); 166 REG_WRITE(ah, AR_Q_TXD, 0); 177 REG_WRITE(ah, AR_Q_TXD, 1 << q); 187 REG_WRITE(a [all...] |
H A D | btcoex.c | 269 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex->bt_coex_mode); 270 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex->bt_coex_mode2); 274 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS0, btcoex->wlan_weight[0]); 275 REG_WRITE(ah, AR_BT_COEX_WL_WEIGHTS1, btcoex->wlan_weight[1]); 277 REG_WRITE(ah, AR_BT_COEX_BT_WEIGHTS(i), 280 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex->bt_coex_weights); 287 REG_WRITE(ah, 0x50040, val); 303 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), 346 REG_WRITE(ah, AR_MCI_COEX_WL_WEIGHTS(i), 356 REG_WRITE(a [all...] |
H A D | ar9003_phy.c | 141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); 150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); 581 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode); 587 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S); 589 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); 605 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 615 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx); 616 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx); 621 REG_WRITE(a [all...] |
H A D | ar9003_rtt.c | 40 REG_WRITE(ah, AR_PHY_RTT_CTRL, 1); 45 REG_WRITE(ah, AR_PHY_RTT_CTRL, 0); 78 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_1_B(chain), val); 83 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); 87 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); 96 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); 150 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val); 154 REG_WRITE(ah, AR_PHY_RTT_TABLE_SW_INTF_B(chain), val);
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