Searched refs:dpll (Results 1 - 25 of 27) sorted by relevance

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/drivers/gpu/drm/gma500/
H A Dpsb_intel_display.c115 u32 dpll = 0, fp = 0, dspcntr, pipeconf; local
162 dpll = DPLL_VGA_MODE_DIS;
164 dpll |= DPLLB_MODE_LVDS;
165 dpll |= DPLL_DVO_HIGH_SPEED;
167 dpll |= DPLLB_MODE_DAC_SERIAL;
171 dpll |= DPLL_DVO_HIGH_SPEED;
172 dpll |=
177 dpll |= (1 << (clock.p1 - 1)) << 16;
180 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
183 dpll |
314 u32 dpll; local
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H A Doaktrail_crtc.c250 temp = REG_READ_WITH_AUX(map->dpll, i);
252 REG_WRITE_WITH_AUX(map->dpll, temp, i);
253 REG_READ_WITH_AUX(map->dpll, i);
256 REG_WRITE_WITH_AUX(map->dpll,
258 REG_READ_WITH_AUX(map->dpll, i);
261 REG_WRITE_WITH_AUX(map->dpll,
263 REG_READ_WITH_AUX(map->dpll, i);
322 temp = REG_READ_WITH_AUX(map->dpll, i);
324 REG_WRITE_WITH_AUX(map->dpll,
326 REG_READ_WITH_AUX(map->dpll,
378 u32 dpll = 0, fp = 0, dspcntr, pipeconf; local
[all...]
H A Dmdfld_intel_display.c275 temp = REG_READ(map->dpll);
281 REG_WRITE(map->dpll, temp);
282 REG_READ(map->dpll);
289 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN);
331 temp = REG_READ(map->dpll);
338 REG_WRITE(map->dpll, temp);
343 REG_WRITE(map->dpll, temp);
344 REG_READ(map->dpll);
348 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
349 REG_READ(map->dpll);
681 u32 dpll = 0, fp = 0; local
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H A Dmdfld_device.c197 pipe->dpll = PSB_RVDC32(map->dpll);
251 u32 dpll; local
258 u32 dpll_val = pipe->dpll;
283 PSB_WVDC32(dpll_val & ~DPLL_VCO_ENABLE, map->dpll);
284 PSB_RVDC32(map->dpll);
289 dpll = PSB_RVDC32(map->dpll);
291 if (!(dpll & DPLL_VCO_ENABLE)) {
295 if (dpll
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H A Dcdv_intel_display.c591 u32 dpll = 0, dspcntr, pipeconf; local
673 dpll = DPLL_VGA_MODE_DIS;
676 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
677 dpll |= 3;
679 /* dpll |= PLL_REF_INPUT_DREFCLK; */
690 dpll |= DPLL_SYNCLOCK_ENABLE;
692 dpll |= DPLLB_MODE_LVDS;
694 dpll |= DPLLB_MODE_DAC_SERIAL; */
695 /* dpll |= (2 << 11); */
736 REG_WRITE(map->dpll, dpl
856 u32 dpll; local
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H A Dgma_display.c226 temp = REG_READ(map->dpll);
228 REG_WRITE(map->dpll, temp);
229 REG_READ(map->dpll);
232 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
233 REG_READ(map->dpll);
236 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
237 REG_READ(map->dpll);
312 temp = REG_READ(map->dpll);
314 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
315 REG_READ(map->dpll);
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H A Doaktrail_hdmi.c281 u32 dspcntr, pipeconf, dpll, temp; local
290 /* Disable dpll if necessary */
291 dpll = REG_READ(DPLL_CTRL);
292 if ((dpll & DPLL_PWRDN) == 0) {
293 REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));
302 /* program and enable dpll */
307 dpll = REG_READ(DPLL_CTRL);
308 dpll &= ~DPLL_PDIV_MASK;
309 dpll &= ~(DPLL_PWRDN | DPLL_RESET);
313 REG_WRITE(DPLL_CTRL, (dpll | (cloc
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H A Dpsb_device.c269 .dpll = DPLL_A,
293 .dpll = DPLL_B,
H A Doaktrail_device.c212 p->dpll = PSB_RVDC32(MRST_DPLL_A);
329 PSB_WVDC32(p->dpll, MRST_DPLL_A);
470 .dpll = MRST_DPLL_A,
494 .dpll = DPLL_B,
H A Dcdv_device.c531 .dpll = DPLL_A,
556 .dpll = DPLL_B,
H A Dmdfld_dsi_pkg_sender.c638 pkg_sender->dpll_reg = map->dpll;
H A Dpsb_drv.h282 u32 dpll; member in struct:psb_offset
316 u32 dpll; member in struct:psb_pipe
/drivers/clk/ti/
H A DMakefile3 clk-common = dpll.o composite.o divider.o gate.o \
/drivers/ata/
H A Dpata_hpt3x2n.c316 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); local
323 if ((flags & USE_DPLL) != dpll && alt->qc_active)
332 int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); local
334 if ((flags & USE_DPLL) != dpll) {
336 flags |= dpll;
339 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
H A Dpata_hpt37x.c982 int dpll, adjust; local
985 dpll = (ppi[0]->udma_mask & 0xC0) ? 3 : 2;
987 f_low = (MHz[clock_slot] * 48) / MHz[dpll];
1015 if (dpll == 3)
1021 MHz[clock_slot], MHz[dpll]);
/drivers/gpu/drm/i915/
H A Dintel_display.c513 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) argument
515 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
1541 u32 dpll = crtc->config.dpll_hw_state.dpll; local
1552 I915_WRITE(reg, dpll);
1563 I915_WRITE(reg, dpll);
1566 I915_WRITE(reg, dpll);
1569 I915_WRITE(reg, dpll);
1629 u32 dpll = crtc->config.dpll_hw_state.dpll; local
5567 pnv_dpll_compute_fp(struct dpll *dpll) argument
5572 i9xx_dpll_compute_fp(struct dpll *dpll) argument
5692 u32 dpll, dpll_md; local
5891 u32 dpll; local
5967 u32 dpll; local
7112 ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) argument
7125 uint32_t dpll; local
7210 u32 dpll = 0, fp = 0, fp2 = 0; local
8837 u32 dpll = pipe_config->dpll_hw_state.dpll; local
8856 u32 dpll = pipe_config->dpll_hw_state.dpll; local
9029 int dpll; local
9072 int dpll; local
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H A Dintel_drv.h231 typedef struct dpll { struct
322 /* Settings for the intel dpll used on pretty much everything but
324 struct dpll dpll; member in struct:intel_crtc_config
326 /* Selected dpll when shared or DPLL_ID_PRIVATE. */
332 /* Actual register state of the dpll, for shared dpll cross-checking. */
343 * Frequence the dpll for the port should run at. Differs from the
870 /* shared dpll functions */
H A Di915_drv.h201 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
202 /* real shared dpll ids must be >= 0 */
212 uint32_t dpll; member in struct:intel_dpll_hw_state
433 struct dpll;
457 struct dpll *match_clock,
458 struct dpll *best_clock);
H A Dintel_dsi.c186 intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV |
H A Dintel_sdvo.c1091 struct dpll *clock = &pipe_config->dpll;
1290 /* done in crtc_mode_set as it lives inside the dpll register */
1377 * the sdvo port register, on all other platforms it is part of the dpll
/drivers/video/fbdev/intelfb/
H A Dintelfbhw.c682 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, argument
688 if (dpll & DPLL_P1_FORCE_DIV2)
691 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
695 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
697 if (dpll & DPLL_P1_FORCE_DIV2)
700 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
701 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
1048 u32 *dpll, *fp0, *fp1; local
1063 dpll = &hw->dpll_b;
1075 dpll
1284 const u32 *dpll, *fp0, *fp1, *pipe_conf; local
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/drivers/ide/
H A Dhpt366.c853 u32 dpll = (f_high << 16) | f_low | 0x100; local
857 pci_write_config_dword(dev, 0x5c, dpll);
874 pci_read_config_dword (dev, 0x5c, &dpll);
875 pci_write_config_dword(dev, 0x5c, (dpll & ~0x100));
/drivers/clk/rockchip/
H A Dclk-rk3188.c26 apll, cpll, dpll, gpll, enumerator in enum:rk3188_plls
198 PNAME(mux_ddrphy_p) = { "dpll", "gpll_ddr" };
210 PNAME(mux_mac_p) = { "gpll", "dpll" };
216 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
H A Dclk-rk3288.c26 apll, dpll, cpll, gpll, npll, enumerator in enum:rk3288_plls
203 [dpll] = PLL(pll_rk3066, PLL_DPLL, "dpll", mux_pll_p, 0, RK3288_PLL_CON(4),
268 GATE(0, "dpll_ddr", "dpll", 0,
/drivers/clk/samsung/
H A Dclk-exynos5420.c147 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll, enumerator in enum:exynos5x_plls
1228 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,

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