Searched refs:offset (Results 1 - 25 of 1060) sorted by last modified time

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/arch/powerpc/platforms/cell/spufs/
H A Dsched.c284 int offset; local
286 offset = -1;
291 ctx->aff_offset = offset--;
294 offset = 0;
298 ctx->aff_offset = offset++;
380 static struct spu *ctx_location(struct spu *ref, int offset, int node) argument
385 if (offset >= 0) {
388 if (offset == 0)
391 offset--;
396 if (offset
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H A Dspu_restore.c83 unsigned int offset; local
92 offset = LSCSA_QW_OFFSET(decr_status);
93 decr_running = regs_spill[offset].slot[0] & SPU_DECR_STATUS_RUNNING;
95 offset = LSCSA_QW_OFFSET(decr);
96 decr = regs_spill[offset].slot[0];
103 unsigned int offset; local
110 offset = LSCSA_QW_OFFSET(ppu_mb);
111 data = regs_spill[offset].slot[0];
117 unsigned int offset; local
124 offset
131 unsigned int offset; local
145 unsigned int offset; local
158 unsigned int offset; local
171 unsigned int offset; local
186 unsigned int offset; local
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H A Dspu_save.c41 unsigned int offset; local
46 offset = LSCSA_QW_OFFSET(event_mask);
47 regs_spill[offset].slot[0] = spu_readch(SPU_RdEventMask);
52 unsigned int offset; local
57 offset = LSCSA_QW_OFFSET(tag_mask);
58 regs_spill[offset].slot[0] = spu_readch(MFC_RdTagMask);
84 unsigned int offset; local
90 offset = LSCSA_QW_OFFSET(fpcr);
91 regs_spill[offset].v = spu_mffpscr();
96 unsigned int offset; local
108 unsigned int offset; local
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/arch/powerpc/platforms/chrp/
H A Dpci.c96 int rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset, argument
100 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
111 int rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset, argument
115 unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
H A Dpegasos_eth.c110 #define MV_READ(offset,val) { val = readl(mv643xx_reg_base + offset); }
111 #define MV_WRITE(offset,data) writel(data, mv643xx_reg_base + offset)
/arch/powerpc/platforms/maple/
H A Dpci.c101 u8 bus, u8 dev_fn, u8 offset)
108 caddr = u3_agp_cfa0(dev_fn, offset);
110 caddr = u3_agp_cfa1(bus, dev_fn, offset);
117 offset &= 0x07;
118 return hose->cfg_data + offset;
122 int offset, int len, u32 *val)
131 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
135 * Note: the caller has already checked that offset is
153 int offset, int len, u32 val)
162 addr = u3_agp_cfg_access(hose, bus->number, devfn, offset);
100 u3_agp_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset) argument
121 u3_agp_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
152 u3_agp_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument
199 u3_ht_cfg_access(struct pci_controller* hose, u8 bus, u8 devfn, u8 offset) argument
210 u3_ht_root_read_config(struct pci_controller *hose, u8 offset, int len, u32 *val) argument
233 u3_ht_root_write_config(struct pci_controller *hose, u8 offset, int len, u32 val) argument
258 u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
296 u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument
356 u4_pcie_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, int offset) argument
375 u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
406 u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument
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/arch/powerpc/platforms/pasemi/
H A Ddma_lib.c54 * @reg: Register to read (offset into PCI CFG space)
63 * @reg: Register to write to (offset into PCI CFG space)
74 * @reg: Register to read (offset into PCI CFG space)
84 * @reg: Register to write to (offset into PCI CFG space)
94 * @reg: Register to read (offset into PCI CFG space)
103 * @reg: Register to write to (offset into PCI CFG space)
170 * @offset: Offset in bytes from start of the total structure to the beginning
182 int total_size, int offset)
194 chan = buf + offset;
181 pasemi_dma_alloc_chan(enum pasemi_dmachan_type type, int total_size, int offset) argument
H A Dpasemi.h9 extern void __iomem *pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset);
H A Dpci.c36 static inline int pa_pxp_offset_valid(u8 bus, u8 devfn, int offset) argument
39 * well, so allow larger offset. It's really a two-function device but the
43 return offset < 8192;
45 return offset < 4096;
49 u8 bus, u8 devfn, int offset)
51 return hose->cfg_data + PA_PXP_CFA(bus, devfn, offset);
67 int offset, int len, u32 *val)
74 if (!is_root_port(bus->number, devfn) || !is_5945_reg(offset))
79 addr = pa_pxp_cfg_addr(hose, bus->number, devfn, offset & ~0x3);
80 byte = offset
48 pa_pxp_cfg_addr(struct pci_controller *hose, u8 bus, u8 devfn, int offset) argument
66 workaround_5945(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
109 pa_pxp_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
146 pa_pxp_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument
234 pasemi_pci_getcfgaddr(struct pci_dev *dev, int offset) argument
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/arch/powerpc/platforms/powermac/
H A Dbootx_init.c472 unsigned long offset = reloc_offset(); local
474 reloc_got2(offset);
592 reloc_got2(-offset);
594 __start(hdr, KERNELBASE + offset, 0);
H A Dnvram.c438 int i, offset; local
447 offset = 0;
451 buffer[i] = ppc_md.nvram_read_val(offset+i);
453 nvram_partitions[pmac_nvram_OF] = offset + 0x10;
455 nvram_partitions[pmac_nvram_XPRAM] = offset + 0x10;
456 nvram_partitions[pmac_nvram_NR] = offset + 0x110;
458 offset += (hdr->len * 0x10);
459 } while(offset < NVRAM_SIZE);
632 int offset = pmac_get_partition(pmac_nvram_XPRAM); local
634 if (offset <
642 int offset = pmac_get_partition(pmac_nvram_XPRAM); local
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H A Dpci.c138 u8 bus, u8 dev_fn, u8 offset)
145 caddr = MACRISC_CFA0(dev_fn, offset);
147 caddr = MACRISC_CFA1(bus, dev_fn, offset);
154 offset &= has_uninorth ? 0x07 : 0x03;
155 return hose->cfg_data + offset;
159 int offset, int len, u32 *val)
167 if (offset >= 0x100)
169 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
173 * Note: the caller has already checked that offset is
191 int offset, in
137 macrisc_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, u8 offset) argument
158 macrisc_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
190 macrisc_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument
232 chaos_validate_dev(struct pci_bus *bus, int devfn, int offset) argument
256 chaos_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
268 chaos_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument
349 u3_ht_cfg_access(struct pci_controller *hose, u8 bus, u8 devfn, u8 offset, int *swap) argument
362 u3_ht_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
413 u3_ht_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument
475 u4_pcie_cfg_access(struct pci_controller* hose, u8 bus, u8 dev_fn, int offset) argument
494 u4_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 *val) argument
526 u4_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int offset, int len, u32 val) argument
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H A Dpfunc_base.c119 unsigned long offset; local
122 offset = *reg;
124 * offset for now too even if it's a bit gross ...
126 if (offset < 0x50)
127 offset += 0x50;
128 offset += (unsigned long)macio->base;
129 pmf_register_driver(gp, &macio_gpio_handlers, (void *)offset);
144 static int macio_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) argument
150 MACIO_OUT32(offset, (MACIO_IN32(offset)
155 macio_do_read_reg32(PMF_STD_ARGS, u32 offset) argument
167 macio_do_write_reg8(PMF_STD_ARGS, u32 offset, u8 value, u8 mask) argument
178 macio_do_read_reg8(PMF_STD_ARGS, u32 offset) argument
190 macio_do_read_reg32_msrx(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift, u32 xor) argument
203 macio_do_read_reg8_msrx(PMF_STD_ARGS, u32 offset, u32 mask, u32 shift, u32 xor) argument
216 macio_do_write_reg32_slm(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask) argument
236 macio_do_write_reg8_slm(PMF_STD_ARGS, u32 offset, u32 shift, u32 mask) argument
278 unin_do_write_reg32(PMF_STD_ARGS, u32 offset, u32 value, u32 mask) argument
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H A Dpfunc_core.c160 u32 offset = pmf_next32(cmd); local
164 LOG_PARSE("pmf: write_reg32(offset: %08x, value: %08x, mask: %08x)\n",
165 offset, value, mask);
167 PMF_PARSE_CALL(write_reg32, cmd, h, offset, value, mask);
172 u32 offset = pmf_next32(cmd); local
174 LOG_PARSE("pmf: read_reg32(offset: %08x)\n", offset);
176 PMF_PARSE_CALL(read_reg32, cmd, h, offset);
182 u32 offset = pmf_next32(cmd); local
186 LOG_PARSE("pmf: write_reg16(offset
194 u32 offset = pmf_next32(cmd); local
204 u32 offset = pmf_next32(cmd); local
216 u32 offset = pmf_next32(cmd); local
234 u32 offset = pmf_next32(cmd); local
246 u32 offset = pmf_next32(cmd); local
258 u32 offset = pmf_next32(cmd); local
309 u32 offset = pmf_next32(cmd); local
320 u32 offset = pmf_next32(cmd); local
332 u32 offset = pmf_next32(cmd); local
406 u32 offset = pmf_next32(cmd); local
420 u32 offset = pmf_next32(cmd); local
433 u32 offset = pmf_next32(cmd); local
447 u32 offset = pmf_next32(cmd); local
460 u32 offset = pmf_next32(cmd); local
473 u32 offset = pmf_next32(cmd); local
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H A Dsetup.c534 int offset = 0; local
576 offset = 0;
578 offset = 1;
583 pr_debug("Found serial console at %s%d\n", devname, offset);
585 return add_preferred_console(devname, offset, NULL);
/arch/powerpc/platforms/powernv/
H A Deeh-ioda.c117 static int ioda_eeh_dbgfs_set(void *data, int offset, u64 val) argument
122 out_be64(phb->regs + offset, val);
126 static int ioda_eeh_dbgfs_get(void *data, int offset, u64 *val) argument
131 *val = in_be64(phb->regs + offset);
H A Dpci-ioda.c1424 pr_devel("cxl release irq range 0x%x: offset: 0x%lx limit: %ld\n",
1425 i, irqs->offset[i],
1427 hwirq = irqs->offset[i] - phb->msi_base;
1455 irqs->offset[i] = phb->msi_base + hwirq;
1457 pr_devel("cxl alloc irq range 0x%x: offset: 0x%lx limit: %li\n",
1458 i, irqs->offset[i], irqs->range[i]);
/arch/powerpc/platforms/ps3/
H A Dmm.c80 * @offset: difference between base and rm.size
87 unsigned long offset; member in struct:mem_region
126 DBG("%s:%d: map.r1.offset = %lxh\n", func, line, m->r1.offset);
141 ? phys_addr : phys_addr + map.r1.offset;
263 r->offset = r->base - map.rm.size;
267 r->size = r->base = r->offset = 0;
291 r->size = r->base = r->offset = 0;
312 r->offset = r->base - map.rm.size;
322 r->size = r->base = r->offset
474 unsigned long offset; local
560 unsigned long offset; local
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H A Dsystem-bus.c566 * comprises a page address and offset into that page. The dma_addr_t
571 unsigned long offset, size_t size, enum dma_data_direction direction,
577 void *ptr = page_address(page) + offset;
593 unsigned long offset, size_t size,
601 void *ptr = page_address(page) + offset;
570 ps3_sb_map_page(struct device *_dev, struct page *page, unsigned long offset, size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) argument
592 ps3_ioc0_map_page(struct device *_dev, struct page *page, unsigned long offset, size_t size, enum dma_data_direction direction, struct dma_attrs *attrs) argument
/arch/powerpc/platforms/pseries/
H A Diommu.c535 unsigned long offset, size; local
537 of_parse_dma_window(dn, dma_window, &tbl->it_index, &offset, &size);
544 tbl->it_offset = offset >> tbl->it_page_shift;
898 * that can map all pages in a linear offset, then setup such a table,
899 * and record the dma-offset in the struct device.
905 * returns the dma offset for use by dma_set_mask
1157 dev_info(dev, "Using 64-bit direct DMA at offset %llx\n", dma_offset);
H A Dmsi.c93 static int rtas_query_irq_number(struct pci_dn *pdn, int offset) argument
104 BUID_HI(buid), BUID_LO(buid), offset);
/arch/powerpc/sysdev/
H A Daxonram.c147 loff_t offset; local
149 offset = sector;
151 offset += device->bd_part->start_sect;
152 offset <<= AXON_RAM_SECTOR_SHIFT;
153 if (offset >= bank->size) {
158 *kaddr = (void *)(bank->ph_addr + offset);
H A Dcpm_common.c138 * This function returns an offset into the muram area.
159 * @offset: The beginning of the chunk as returned by cpm_muram_alloc().
161 int cpm_muram_free(unsigned long offset) argument
167 ret = rh_free(&cpm_muram_info, offset);
176 * @offset: the offset into the muram area to reserve
183 unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size) argument
190 start = rh_alloc_fixed(&cpm_muram_info, offset, size, "commproc");
198 * cpm_muram_addr - turn a muram offset into a virtual address
199 * @offset
201 cpm_muram_addr(unsigned long offset) argument
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H A Dfsl_85xx_cache_sram.c41 unsigned long offset; local
60 offset = rh_alloc_align(cache_sram->rh, size, align, NULL);
63 if (IS_ERR_VALUE(offset))
66 *phys = cache_sram->base_phys + offset;
68 return (unsigned char *)cache_sram->base_virt + offset;
H A Dfsl_msi.c341 int offset, int irq_index)
359 cascade_data->index = offset;
375 msi_hwirq(msi, offset, i), 1);
390 u32 offset; local
438 * First read the MSIIR/MSIIR1 offset from dts
439 * On failure use the hardcode MSIIR offset
508 offset = p[i * 2] / IRQS_PER_MSI_REG;
512 err = fsl_msi_setup_hwirq(msi, dev, offset + j,
340 fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev, int offset, int irq_index) argument

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