Searched defs:reg1 (Results 1 - 25 of 30) sorted by relevance

12

/drivers/media/dvb/frontends/
H A Dtua6100.c77 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; local
80 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 };
95 reg1[1] = 0x2c;
97 reg1[1] = 0x0c;
100 reg1[1] |= 0x40;
102 reg1[1] |= 0x80;
120 reg1[1] |= (div >> 9) & 0x03;
121 reg1[2] = div >> 1;
122 reg1[3] = (div << 7);
126 reg1[
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H A Ds5h1409.c568 u16 reg, reg1, reg2; local
583 reg1 = s5h1409_readreg(state, 0xb2);
588 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
606 u16 reg, reg1, reg2; local
614 reg1 = s5h1409_readreg(state, 0xb2);
619 (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff)));
H A Dstv0297.c107 static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len) argument
111 &reg1,.len = 1},
118 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
122 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
127 dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret);
H A Dtda8083.c76 static int tda8083_readregs (struct tda8083_state* state, u8 reg1, u8 *b, u8 len) argument
79 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = &reg1, .len = 1 },
86 __func__, reg1, ret);
H A Dm88rs2000.c225 u8 reg0, reg1; local
230 reg1 = m88rs2000_demod_read(state, 0xb2);
232 m88rs2000_demod_write(state, 0xb2, reg1);
242 u8 reg0, reg1; local
245 reg1 = m88rs2000_demod_read(state, 0xb2);
247 reg1 &= 0x3f;
255 reg1 |= 0x80;
260 m88rs2000_demod_write(state, 0xb2, reg1);
H A Dstv0299.c123 static int stv0299_readregs (struct stv0299_state* state, u8 reg1, u8 *b, u8 len) argument
126 struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = &reg1, .len = 1 },
H A Dsi21xx.c227 static int si21_writeregs(struct si21xx_state *state, u8 reg1, argument
231 u8 buf[60];/* = { reg1, data };*/
239 msg.buf[0] = reg1;
245 dprintk("%s: writereg error (reg1 == 0x%02x, data == 0x%02x, "
246 "ret == %i)\n", __func__, reg1, data[0], ret);
309 static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len) argument
316 .buf = &reg1,
483 u8 reg1; local
490 reg1 = serit_sp1511lhb_inittab[i];
492 if (reg1
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/drivers/ata/
H A Dpata_hpt366.c357 u32 reg1; local
371 pci_read_config_dword(dev, 0x40, &reg1);
375 switch ((reg1 & 0x700) >> 8) {
H A Dpata_macio.c260 u32 reg1; /* Bits to set in first timing reg */ member in struct:pata_macio_timing
416 priv->treg[adev->devno][0] |= t->reg1;
420 if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) {
427 priv->treg[adev->devno][0] |= t->reg1;
/drivers/ide/
H A Dali14xx.c72 static struct { u8 reg1, reg2, reg3, reg4; } regTab[4] = { member in struct:__anon891
138 outReg(param1, regTab[driveNum].reg1);
/drivers/net/tokenring/
H A Dmadgemc.c411 int pending,reg1; local
437 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
438 outb(reg1 ^ MC_CONTROL_REG1_SINTEN,
440 outb(reg1, dev->base_addr + MC_CONTROL_REG1);
465 unsigned char reg1; local
468 reg1 = inb(dev->base_addr + MC_CONTROL_REG1);
471 reg1 |= MC_CONTROL_REG1_SPEED_SEL; /* add for 16mb */
472 else if (reg1 & MC_CONTROL_REG1_SPEED_SEL)
473 reg1 ^= MC_CONTROL_REG1_SPEED_SEL; /* remove for 4mb */
474 outb(reg1, de
492 static int reg1; local
535 unsigned int reg1; local
621 unsigned char reg0, reg1, tmpreg0, i; local
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/drivers/power/
H A Dwm831x_power.c220 int ret, reg1, reg2; local
230 reg1 = 0;
238 reg1 |= WM831X_CHG_ENA;
242 reg1 |= WM831X_CHG_FAST;
258 pdata->eoc_iterm, &reg1,
275 reg1);
/drivers/staging/keucr/
H A Dsmilecc.c102 BYTE reg1; /* D-all,CP5,CP4,CP3,... */ local
106 reg1 = reg2 = reg3 = 0; /* Clear parameter */
109 reg1 ^= (a&MASK_CPS); /* XOR with a */
120 *ecc3 = ((~reg1)<<2)|BIT1BIT0; /* Make TEL format */
/drivers/net/ethernet/8390/
H A Dwd.c243 outb(tmp, ioaddr+1); /* Restore original reg1 value. */
278 int reg1 = inb(ioaddr+1); local
280 if (ancient || reg1 == 0xff) { /* Ack!! No way to read the IRQ! */
305 dev->irq = irqmap[((reg4 >> 5) & 0x03) + (reg1 & 0x04)];
/drivers/gpu/drm/nouveau/
H A Dnouveau_hw.c200 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) argument
202 bool head_a = (reg1 == NV_PRAMDAC_VPLL_COEFF);
215 setPLL_double_highregs(struct drm_device *dev, uint32_t reg1, argument
221 uint32_t reg2 = reg1 + ((reg1 == NV_RAMDAC_VPLL2) ? 0x5c : 0x70);
222 uint32_t oldpll1 = NVReadRAMDAC(dev, 0, reg1);
229 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
237 if (chip_version > 0x40 && reg1 >= NV_PRAMDAC_VPLL_COEFF) { /* !nv40 */
239 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
263 switch (reg1) {
373 nouveau_hw_setpll(struct drm_device *dev, uint32_t reg1, struct nouveau_pll_vals *pv) argument
394 nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, uint32_t pll2, struct nouveau_pll_vals *pllvals) argument
430 uint32_t reg1 = get_pll_register(dev, plltype), pll1, pll2 = 0; local
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H A Dnv50_crtc.c334 uint32_t reg1, reg2; local
349 reg1 = nv_rd32(dev, pll.reg + 4) & 0xff00ff00;
352 nv_wr32(dev, pll.reg + 4, reg1 | (M1 << 16) | N1);
363 reg1 = nv_rd32(dev, pll.reg + 4) & 0xffc00000;
365 nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
/drivers/net/irda/
H A Dnsc-ircc.c875 int reg1, reg2, irq, irqt, dma1, dma2; local
890 reg1 = inb(cfg_base+1);
893 info->fir_base = (reg1 << 8) | reg2;
913 IRDA_DEBUG(2, "%s(): io=0x%02x%02x, irq=%d (type %d), rxdma=%d, txdma=%d, enabled=%d (suspended=%d)\n", __func__, reg1,reg2,irq,irqt,dma1,dma2,enabled,susp);
/drivers/staging/rts_pstor/
H A Drtsx_card.c101 u8 reg1 = 0, reg2 = 0; local
103 rtsx_read_register(chip, 0xFF34, &reg1);
105 RTSX_DEBUGP("reg 0xFF34: 0x%x, reg 0xFF38: 0x%x\n", reg1, reg2);
106 if ((reg1 & 0xC0) && (reg2 & 0xC0)) {
H A Drtsx_chip.c1104 u8 reg0 = 0, reg1 = 0; local
1115 reg1 = (u8)tmp;
1116 if (chip->aspm_level[1] != reg1) {
1118 chip->aspm_level[1] = reg1;
1121 if ((reg0 & 0x03) && (reg1 & 0x03)) {
/drivers/staging/xgifb/
H A DXGI_main_26.c1096 /* unsigned char reg, reg1; */
1884 u8 reg, reg1; local
1933 reg1 = xgifb_reg_get(XGISR, IND_SIS_PASSWORD);
1935 if (reg1 != 0xa1) { /*I/O error */
2056 reg1 = xgifb_reg_get(XGIPART4, 0x23);
2073 reg1 = xgifb_reg_get(XGIPART4, 0x23);
/drivers/video/i810/
H A Di810_main.c401 u32 reg1; local
404 reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27);
407 reg1 |= 0x8000 | par->pixconf;
409 i810_writel(PIXCONF, mmio, reg1);
/drivers/edac/
H A Damd64_edac.c874 int reg1 = DCSB1 + (cs * 4); local
885 if (!amd64_read_dct_pci_cfg(pvt, reg1, base1))
887 cs, *base1, reg1);
892 int reg1 = DCSM1 + (cs * 4); local
903 if (!amd64_read_dct_pci_cfg(pvt, reg1, mask1))
905 cs, *mask1, reg1);
/drivers/net/wan/
H A Dpc300_drv.c3291 u8 reg1; local
3294 reg1 = cpc_readb(card->hw.falcbase + CPLD_REG1);
3295 cpc_writeb(card->hw.falcbase + CPLD_REG1, (reg1 + 0x5a));
3296 if (cpc_readb(card->hw.falcbase + CPLD_REG1) == reg1) {
3306 cpc_writeb(card->hw.falcbase + CPLD_REG1, reg1);
/drivers/hwmon/
H A Dw83795.c307 u8 reg0, reg1; local
322 reg1 = SENSORS_LIMIT(DIV_ROUND_CLOSEST(base_clock, val), 1, 128);
323 best1 = base_clock / reg1;
324 reg1 = 0x80 | (reg1 - 1);
328 return reg1;
/drivers/net/ethernet/qlogic/
H A Dqla3xxx.c976 u16 reg1; local
983 err = ql_mii_read_reg(qdev, PHY_ID_0_REG, &reg1);
996 if ((reg1 == 0xffff) || (reg2 == 0xffff)) {
1005 err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, &reg1, miiAddr);
1024 qdev->phyType = getPhyType(qdev, reg1, reg2);

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