/drivers/mtd/onenand/ |
H A D | onenand_sim.c | 66 void __iomem *base; member in struct:onenand_flash 75 (this->base + ONENAND_DATARAM + offset) 78 (this->base + ONENAND_SPARERAM + offset) 81 (readw(this->base + ONENAND_REG_WP_STATUS)) 84 (writew(v, this->base + ONENAND_REG_WP_STATUS)) 177 writew(manuf_id, this->base); 178 writew(device_id, this->base + 2); 179 writew(version_id, this->base + 4); 222 writew(interrupt, this->base + ONENAND_REG_INTERRUPT); 281 die = readw(this->base [all...] |
/drivers/net/wireless/brcm80211/brcmfmac/ |
H A D | sdio_chip.h | 24 #define CORE_CC_REG(base, field) \ 25 (base + offsetof(struct chipcregs, field)) 26 #define CORE_BUS_REG(base, field) \ 27 (base + offsetof(struct sdpcmd_regs, field)) 28 #define CORE_SB(base, field) \ 29 (base + SBCONFIGOFF + offsetof(struct sbconfig, field)) 60 u32 base; member in struct:chip_core_info
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/drivers/gpu/drm/nouveau/ |
H A D | nv04_cursor.c | 11 nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, true); 17 nv_show_cursor(nv_crtc->base.dev, nv_crtc->index, false); 24 NVWriteRAMDAC(nv_crtc->base.dev, nv_crtc->index, 40 struct drm_device *dev = nv_crtc->base.dev; 43 struct drm_crtc *crtc = &nv_crtc->base;
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/drivers/scsi/ |
H A D | t128.h | 113 void __iomem *base 116 void __iomem *base 119 base = ((struct NCR5380_hostdata *)(instance->hostdata))->base 121 #define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20))
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H A D | nsp32.c | 439 unsigned int base = SCpnt->host->io_port; 447 nsp32_write2(base, TIMER_SET, time & TIMER_CNT_MASK); 458 unsigned int base = SCpnt->device->host->io_port; local 472 phase = nsp32_read1(base, SCSI_BUS_MONITOR); 509 // nsp_dbg(NSP32_DEBUG_AUTOSCSI, "sel time out=0x%x\n", nsp32_read2(base, SEL_TIME_OUT)); 510 // nsp32_write2(base, SEL_TIME_OUT, SEL_TIMEOUT_TIME); 570 nsp32_write4(base, SGT_ADR, data->auto_paddr); 571 nsp32_write2(base, COMMAND_CONTROL, CLEAR_CDB_FIFO_POINTER | 577 ret = nsp32_arbitration(SCpnt, base); 589 unsigned int base local 761 nsp32_arbitration(struct scsi_cmnd *SCpnt, unsigned int base) argument 814 unsigned int base = SCpnt->device->host->io_port; local 1056 unsigned int base = data->BaseAddress; local 1164 unsigned int base = data->BaseAddress; local 1461 unsigned int base; local 1556 unsigned int base = SCpnt->device->host->io_port; local 1594 unsigned int base = SCpnt->device->host->io_port; local 1825 unsigned int base = SCpnt->device->host->io_port; local 1901 unsigned int base = data->BaseAddress; local 1969 unsigned int base = SCpnt->device->host->io_port; local 2499 unsigned int base = data->BaseAddress; local 2528 unsigned int base = data->BaseAddress; local 2559 unsigned int base = data->BaseAddress; local 2572 unsigned int base = data->BaseAddress; local 2854 unsigned int base = SCpnt->device->host->io_port; local 2882 unsigned int base = SCpnt->device->host->io_port; local 2899 unsigned int base = data->BaseAddress; local 2942 unsigned int base = SCpnt->device->host->io_port; local 3245 int base = data->BaseAddress; local 3263 int base = data->BaseAddress; local [all...] |
H A D | imm.c | 36 int base; /* Actual port address */ member in struct:__anon4402 51 static void imm_reset_pulse(unsigned int base); 65 dev->base = dev->dev->port->base; 192 unsigned short ppb = dev->base; 206 * STR register (LPT base+1) to SCSI mapping: 248 unsigned short base = tmp->base; local 262 w_ctr(base, 0x04); 264 w_dtr(base, mod 314 imm_byte_out(unsigned short base, const char *buffer, int len) argument 329 imm_nibble_in(unsigned short base, char *buffer, int len) argument 348 imm_byte_in(unsigned short base, char *buffer, int len) argument 994 imm_reset_pulse(unsigned int base) argument [all...] |
/drivers/pci/hotplug/ |
H A D | cpqphp_pci.c | 541 * Saves the length of all base address registers for the 554 u32 base; local 588 * IO and memory base lengths 593 pci_bus_read_config_dword (pci_bus, devfn, cloop, &base); 595 if (base) { 596 if (base & 0x01L) { 597 /* IO base 598 * set base = amount of IO space 601 base = base 697 u32 base; local 1031 u32 base; local [all...] |
/drivers/gpio/ |
H A D | gpio-omap.c | 56 void __iomem *base; member in struct:gpio_bank 98 return gpio_irq - bank->irq_base + bank->chip.base; 103 void __iomem *reg = bank->base; 120 void __iomem *reg = bank->base; 137 void __iomem *reg = bank->base + bank->regs->dataout; 152 void __iomem *reg = bank->base + bank->regs->datain; 159 void __iomem *reg = bank->base + bank->regs->dataout; 164 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) argument 166 int l = __raw_readl(base + reg); 173 __raw_writel(l, base 253 void __iomem *base = bank->base; local 337 void __iomem *base = bank->base; local 592 void __iomem *base = bank->base; local 956 void __iomem *base = bank->base; local 1160 void __iomem *base = bank->base; local 1185 void __iomem *base = bank->base; local [all...] |
/drivers/staging/vme/bridges/ |
H A D | vme_ca91cx42.c | 104 val = ioread32(bridge->base + DGCS); 121 val = ioread32(bridge->base + DGCS); 142 vec = ioread32(bridge->base + 164 enable = ioread32(bridge->base + LINT_EN); 165 stat = ioread32(bridge->base + LINT_STAT); 193 iowrite32(serviced, bridge->base + LINT_STAT); 215 iowrite32(0, bridge->base + VINT_EN); 218 iowrite32(0, bridge->base + LINT_EN); 220 iowrite32(0x00FFFFFF, bridge->base + LINT_STAT); 231 iowrite32(0, bridge->base [all...] |
/drivers/i2c/busses/ |
H A D | i2c-highlander.c | 46 void __iomem *base; member in struct:highlander_i2c_dev 60 iowrite16(ioread16(dev->base + SMCR) | SMCR_IEIC, dev->base + SMCR); 65 iowrite16(ioread16(dev->base + SMCR) & ~SMCR_IEIC, dev->base + SMCR); 70 iowrite16(ioread16(dev->base + SMCR) | SMCR_START, dev->base + SMCR); 75 iowrite16(ioread16(dev->base + SMCR) | SMCR_IRIC, dev->base + SMCR); 82 smmr = ioread16(dev->base [all...] |
H A D | i2c-nforce2.c | 69 int base; member in struct:nforce2_smbus 87 #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */ 88 #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */ 89 #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */ 90 #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */ 91 #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */ 92 #define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data 94 #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to 97 #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */ 338 smbus->base [all...] |
H A D | i2c-versatile.c | 30 void __iomem *base; member in struct:i2c_versatile 37 writel(SDA, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); 44 writel(SCL, i2c->base + (state ? I2C_CONTROLS : I2C_CONTROLC)); 50 return !!(readl(i2c->base + I2C_CONTROL) & SDA); 56 return !!(readl(i2c->base + I2C_CONTROL) & SCL); 91 i2c->base = ioremap(r->start, resource_size(r)); 92 if (!i2c->base) { 97 writel(SCL | SDA, i2c->base + I2C_CONTROLS); 120 iounmap(i2c->base);
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/drivers/mtd/nand/ |
H A D | jz4740_nand.c | 62 void __iomem *base; member in struct:jz_nand 92 reg = readl(nand->base + JZ_REG_NAND_CTRL); 97 writel(reg, nand->base + JZ_REG_NAND_CTRL); 114 writel(0, nand->base + JZ_REG_NAND_IRQ_STAT); 115 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); 134 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); 151 status = readl(nand->base + JZ_REG_NAND_IRQ_STAT); 157 reg = readl(nand->base + JZ_REG_NAND_ECC_CTRL); 159 writel(reg, nand->base + JZ_REG_NAND_ECC_CTRL); 162 ecc_code[i] = readb(nand->base 254 jz_nand_ioremap_resource(struct platform_device *pdev, const char *name, struct resource **res, void __iomem **base) argument [all...] |
/drivers/input/keyboard/ |
H A D | omap4-keypad.c | 74 void __iomem *base; member in struct:omap4_keypad 95 keypad_data->base + OMAP4_KBD_IRQENABLE); 97 *new_state = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE31_0); 98 *(new_state + 1) = __raw_readl(keypad_data->base 124 __raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS), 125 keypad_data->base + OMAP4_KBD_IRQSTATUS); 129 keypad_data->base + OMAP4_KBD_IRQENABLE); 143 keypad_data->base + OMAP4_KBD_CTRL); 145 keypad_data->base + OMAP4_KBD_DEBOUNCINGTIME); 147 keypad_data->base [all...] |
/drivers/mmc/host/ |
H A D | davinci_mmc.c | 183 void __iomem *base; member in struct:mmc_davinci_host 267 writel(*((u32 *)p), host->base + DAVINCI_MMCDXR); 271 iowrite8_rep(host->base + DAVINCI_MMCDXR, p, (n & 3)); 276 *((u32 *)p) = readl(host->base + DAVINCI_MMCDRR); 280 ioread8_rep(host->base + DAVINCI_MMCDRR, p, (n & 3)); 366 writel(0x1FFF, host->base + DAVINCI_MMCTOR); 389 writel(cmd->arg, host->base + DAVINCI_MMCARGHL); 390 writel(cmd_reg, host->base + DAVINCI_MMCCMD); 404 writel(im_val, host->base + DAVINCI_MMCIM); 669 writel(0, host->base [all...] |
H A D | omap_hsmmc.c | 128 #define OMAP_HSMMC_READ(base, reg) \ 129 __raw_readl((base) + OMAP_HSMMC_##reg) 131 #define OMAP_HSMMC_WRITE(base, reg, val) \ 132 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 156 void __iomem *base; member in struct:omap_hsmmc_host 436 OMAP_HSMMC_WRITE(host->base, SYSCTL, 437 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 445 OMAP_HSMMC_WRITE(host->base, SYSCTL, 446 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 447 if ((OMAP_HSMMC_READ(host->base, SYSCT [all...] |
H A D | mmci.c | 129 writel(clk, host->base + MMCICLOCK); 140 writel(pwr, host->base + MMCIPOWER); 197 writel(0, host->base + MMCICOMMAND); 212 void __iomem *base = host->base; local 215 unsigned int mask0 = readl(base + MMCIMASK0); 220 writel(mask0, base + MMCIMASK0); 223 writel(mask, base + MMCIMASK1); 228 writel(0, host->base + MMCIDATACTRL); 350 status = readl(host->base 612 void __iomem *base; local 683 void __iomem *base = host->base; local 777 void __iomem *base = host->base; local 807 void __iomem *base = host->base; local 856 void __iomem *base = host->base; local 912 void __iomem *base = host->base; local [all...] |
/drivers/gpu/drm/vmwgfx/ |
H A D | vmwgfx_ldu.c | 32 container_of(x, struct vmw_legacy_display_unit, base.crtc) 34 container_of(x, struct vmw_legacy_display_unit, base.encoder) 36 container_of(x, struct vmw_legacy_display_unit, base.connector) 51 struct vmw_display_unit base; member in struct:vmw_legacy_display_unit 59 vmw_display_unit_cleanup(&ldu->base); 88 crtc = &entry->base.crtc; 96 fb = entry->base.crtc.fb; 104 fb = entry->base.crtc.fb; 116 crtc = &entry->base.crtc; 136 du = &entry->base; [all...] |
/drivers/scsi/aacraid/ |
H A D | comminit.c | 52 unsigned char *base; local 67 base = pci_alloc_consistent(dev->pdev, size, &phys); 69 if(base == NULL) 74 dev->comm_addr = (void *)base; 79 dev->host_rrq = (u32 *)(base + fibsize); 84 dev->init = (struct aac_init *)(base + fibsize + host_rrq_size); 99 dev->aif_base_va = (struct hw_fib *)base; 140 * Increment the base address by the amount already used 142 base = base [all...] |
/drivers/ide/ |
H A D | gayle.c | 34 * These are at different offsets from the base 79 static void __init gayle_setup_ports(struct ide_hw *hw, unsigned long base, argument 86 hw->io_ports.data_addr = base; 89 hw->io_ports_array[i] = base + 2 + i * 4; 121 unsigned long base, ctrlport, irqport; local 140 base = (unsigned long)ZTWO_VADDR(pdata->base); 148 for (i = 0; i < GAYLE_NUM_PROBE_HWIFS; i++, base += GAYLE_NEXT_PORT) { 150 ctrlport = base + GAYLE_CONTROL; 152 gayle_setup_ports(&hw[i], base, ctrlpor [all...] |
/drivers/net/ethernet/nvidia/ |
H A D | forcedeth.c | 751 /* in dev: base, irq */ 793 void __iomem *base; member in struct:fe_priv 946 return ((struct fe_priv *)netdev_priv(dev))->base; 949 static inline void pci_push(u8 __iomem *base) argument 952 readl(base); 976 u8 __iomem *base = get_hwbase(dev); local 978 pci_push(base); 984 } while ((readl(base + offset) & mask) != target); 1004 u8 __iomem *base = get_hwbase(dev); local 1008 writel(dma_low(np->ring_addr), base 1055 u8 __iomem *base = get_hwbase(dev); local 1104 u8 __iomem *base = get_hwbase(dev); local 1112 u8 __iomem *base = get_hwbase(dev); local 1144 u8 __iomem *base = get_hwbase(dev); local 1229 u8 __iomem *base = get_hwbase(dev); local 1389 u8 __iomem *base = get_hwbase(dev); local 1534 u8 __iomem *base = get_hwbase(dev); local 1555 u8 __iomem *base = get_hwbase(dev); local 1576 u8 __iomem *base = get_hwbase(dev); local 1589 u8 __iomem *base = get_hwbase(dev); local 1623 u8 __iomem *base = get_hwbase(dev); local 1635 u8 __iomem *base = get_hwbase(dev); local 1666 u8 __iomem *base = get_hwbase(dev); local 2065 u8 __iomem *base = get_hwbase(dev); local 2114 u8 __iomem *base = get_hwbase(dev); local 2585 u8 __iomem *base = get_hwbase(dev); local 2954 u8 __iomem *base = get_hwbase(dev); local 2999 u8 __iomem *base = get_hwbase(dev); local 3055 u8 __iomem *base = get_hwbase(dev); local 3115 u8 __iomem *base = get_hwbase(dev); local 3152 u8 __iomem *base = get_hwbase(dev); local 3230 u8 __iomem *base = get_hwbase(dev); local 3470 u8 __iomem *base = get_hwbase(dev); local 3487 u8 __iomem *base = np->base; local 3526 u8 __iomem *base = get_hwbase(dev); local 3560 u8 __iomem *base = get_hwbase(dev); local 3589 u8 __iomem *base = get_hwbase(dev); local 3630 u8 __iomem *base = get_hwbase(dev); local 3701 u8 __iomem *base = get_hwbase(dev); local 3746 u8 __iomem *base = get_hwbase(dev); local 3813 u8 __iomem *base = get_hwbase(dev); local 3838 u8 __iomem *base = get_hwbase(dev); local 3863 u8 __iomem *base = get_hwbase(dev); local 4001 u8 __iomem *base = get_hwbase(dev); local 4155 u8 __iomem *base = get_hwbase(dev); local 4431 u8 __iomem *base = get_hwbase(dev); local 4503 u8 __iomem *base = get_hwbase(dev); local 4780 u8 __iomem *base = get_hwbase(dev); local 4865 u8 __iomem *base = get_hwbase(dev); local 4894 u8 __iomem *base = get_hwbase(dev); local 4957 u8 __iomem *base = get_hwbase(dev); local 5079 u8 __iomem *base = get_hwbase(dev); local 5190 u8 __iomem *base = get_hwbase(dev); local 5225 u8 __iomem *base = get_hwbase(dev); local 5241 u8 __iomem *base = get_hwbase(dev); local 5270 u8 __iomem *base = get_hwbase(dev); local 5442 u8 __iomem *base; local 5525 u8 __iomem *base; local 5979 u8 __iomem *base = get_hwbase(dev); local 6018 u8 __iomem *base = get_hwbase(dev); local 6039 u8 __iomem *base = get_hwbase(dev); local [all...] |
/drivers/input/serio/ |
H A D | sa1111ps2.c | 49 void __iomem *base; member in struct:ps2if 67 status = sa1111_readl(ps2if->base + PS2STAT); 70 sa1111_writel(PS2STAT_STP, ps2if->base + PS2STAT); 75 scancode = sa1111_readl(ps2if->base + PS2DATA) & 0xff; 82 status = sa1111_readl(ps2if->base + PS2STAT); 97 status = sa1111_readl(ps2if->base + PS2STAT); 102 sa1111_writel(ps2if->buf[ps2if->tail], ps2if->base + PS2DATA); 125 if (sa1111_readl(ps2if->base + PS2STAT) & PS2STAT_TXE) { 126 sa1111_writel(val, ps2if->base + PS2DATA); 173 sa1111_writel(PS2CR_ENA, ps2if->base [all...] |
/drivers/video/ |
H A D | sh_mobile_meram.c | 142 * @base: Registers base address 151 void __iomem *base; member in struct:sh_mobile_meram_priv 171 #define MERAM_ICB_OFFSET(base, idx, off) ((base) + (off) + (idx) * 0x20) 173 static inline void meram_write_icb(void __iomem *base, unsigned int idx, argument 176 iowrite32(val, MERAM_ICB_OFFSET(base, idx, off)); 179 static inline unsigned long meram_read_icb(void __iomem *base, unsigned int idx, argument 182 return ioread32(MERAM_ICB_OFFSET(base, idx, off)); 185 static inline void meram_write_reg(void __iomem *base, unsigne argument 191 meram_read_reg(void __iomem *base, unsigned int off) argument [all...] |
/drivers/watchdog/ |
H A D | f71808e_wdt.c | 126 static inline int superio_inb(int base, int reg); 127 static inline int superio_inw(int base, int reg); 128 static inline void superio_outb(int base, int reg, u8 val); 129 static inline void superio_set_bit(int base, int reg, int bit); 130 static inline void superio_clear_bit(int base, int reg, int bit); 131 static inline int superio_enter(int base); 132 static inline void superio_select(int base, int ld); 133 static inline void superio_exit(int base); 156 static inline int superio_inb(int base, int reg) argument 158 outb(reg, base); 162 superio_inw(int base, int reg) argument 170 superio_outb(int base, int reg, u8 val) argument 176 superio_set_bit(int base, int reg, int bit) argument 183 superio_clear_bit(int base, int reg, int bit) argument 190 superio_enter(int base) argument 205 superio_select(int base, int ld) argument 211 superio_exit(int base) argument [all...] |
/drivers/net/ethernet/natsemi/ |
H A D | ns83820.c | 427 u8 __iomem *base; member in struct:ns83820 470 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR) 480 dev->base + RXDP); 621 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 625 tbisr = readl(dev->base + TBISR); 626 tanar = readl(dev->base + TANAR); 627 tanlpar = readl(dev->base + TANLPAR); 635 writel(readl(dev->base + TXCFG) 637 dev->base + TXCFG); 638 writel(readl(dev->base 1192 u8 __iomem *base = dev->base; local [all...] |