/drivers/gpu/drm/radeon/ |
H A D | radeon_legacy_tv.c | 18 * Unit for hPos (in TV clock periods) 246 pll = &rdev->clock.p2pll; 248 pll = &rdev->clock.p1pll; 438 pll = &rdev->clock.p2pll; 440 pll = &rdev->clock.p1pll; 480 /* Convert hOffset from n. of TV clock periods to n. of CRTC clock periods (CRTC pixels) */
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H A D | radeon_pm.c | 214 /* set engine clock */ 223 /* set memory clock */ 611 rdev->pm.default_sclk = rdev->clock.default_sclk; 612 rdev->pm.default_mclk = rdev->clock.default_mclk; 613 rdev->pm.current_sclk = rdev->clock.default_sclk; 614 rdev->pm.current_mclk = rdev->clock.default_mclk; 870 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 871 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 872 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 874 seq_printf(m, "current memory clock [all...] |
/drivers/media/video/omap3isp/ |
H A D | isp.h | 150 * @cam_ick: Pointer to camera interface clock structure. 151 * @cam_mclk: Pointer to camera functional clock structure. 152 * @dpll4_m5_ck: Pointer to DPLL4 M5 clock structure. 153 * @csi2_fck: Pointer to camera CSI2 complexIO clock structure. 154 * @l3_ick: Pointer to OMAP3 L3 bus interface clock. 197 struct clk *clock[5]; member in struct:isp_device
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H A D | ispresizer.c | 493 * functional clock or 100 MP/s, whichever is lower. According to the TRM 497 * output data rate to the functional clock or 200 MP/s, whichever is lower, 503 * max intermediate rate <= L3 clock * input height / output height 504 * max intermediate rate <= L3 clock / 2 520 unsigned long clock; local 522 clock = div_u64((u64)limit * res->crop.active.height, ofmt->height); 523 clock = min(clock, limit / 2); 524 *max_rate = div_u64((u64)clock * res->crop.active.width, ofmt->width); 552 * The number of cycles per second is controlled by the L3 clock, leadin [all...] |
/drivers/media/video/s5p-mfc/ |
H A D | s5p_mfc_common.h | 171 struct clk *clock; member in struct:s5p_mfc_pm
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/drivers/mfd/ |
H A D | twl-core.c | 1105 * These three functions initialize the on-chip clock framework, 1133 struct twl4030_clock_init_data *clock) 1147 printk(KERN_WARNING "Skipping twl internal clock init and " 1156 /* REVISIT for non-OMAP systems, pass the clock rate from 1161 printk(KERN_WARNING "Skipping twl internal clock init and " 1180 if (clock && clock->ck32k_lowpwr_enable) 1189 pr_err("%s: clock init err [%d]\n", DRIVER_NAME, e); 1290 /* setup clock framework */ 1291 clocks_init(&client->dev, pdata->clock); 1132 clocks_init(struct device *dev, struct twl4030_clock_init_data *clock) argument [all...] |
/drivers/mmc/host/ |
H A D | at91_mci.c | 22 This configures the device to put it into the correct mode and clock speed 713 if (ios->clock == 0) { 722 if ((at91_master_clock % (ios->clock * 2)) == 0) 723 clkdiv = ((at91_master_clock / ios->clock) / 2) - 1; 725 clkdiv = (at91_master_clock / ios->clock) / 2; 739 /* Set the clock divider */ 1037 clk_enable(host->mci_clk); /* Enable the peripheral clock */ 1139 clk_disable(host->mci_clk); /* Disable the peripheral clock */
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H A D | pxamci.c | 12 * - Have to turn off the clock whenever we touch the device. 149 dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); 469 if (ios->clock) { 471 unsigned int clk = rate / ios->clock; 476 if (ios->clock == 26000000) { 489 if (rate / clk > ios->clock) 637 * Calculate minimum clock rate, rounding up.
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H A D | sdhci-pltfm.c | 82 clk = of_get_property(np, "clock-frequency", &size); 84 pltfm_host->clock = be32_to_cpup(clk);
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H A D | dw_mmc.c | 81 * @clock: Clock rate configured by set_ios(). Protected by host->lock. 95 unsigned int clock; member in struct:dw_mci_slot 619 if (slot->clock != host->current_speed) { 620 if (host->bus_hz % slot->clock) 625 div = ((host->bus_hz / slot->clock) >> 1) + 1; 627 div = (host->bus_hz / slot->clock) >> 1; 631 " div = %d)\n", slot->id, host->bus_hz, slot->clock, 634 /* disable clock */ 642 /* set clock to desired speed */ 649 /* enable clock */ [all...] |
/drivers/net/can/sja1000/ |
H A D | ems_pci.c | 90 * You will probably also want to set the clock divider value to 7 324 priv->can.clock.freq = EMS_PCI_CAN_CLOCK;
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H A D | ems_pcmcia.c | 58 * You will probably also want to set the clock divider value to 7 225 priv->can.clock.freq = EMS_PCMCIA_CAN_CLOCK;
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/drivers/net/wan/ |
H A D | pc300.h | 39 * New configuration parameters (line code, CRC calculation and clock). 85 * Inclusion of 'clock' field on structure 'pc300hw'. 311 u32 clock; /* Board clock */ member in struct:pc300hw
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/drivers/scsi/ |
H A D | NCR_D700.c | 56 * featured and uses the clock algorithm to keep track of outstanding 201 hostdata->clock = NCR_D700_CLOCK_MHZ;
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/drivers/staging/crystalhd/ |
H A D | crystalhd_cmds.c | 729 struct BC_CLOCK *clock; local 738 clock = &idata->udata.u.clockValue; 740 ctx->hw_ctx.core_clock_mhz = clock->clk; 748 clock->clk = ctx->hw_ctx.core_clock_mhz;
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/drivers/video/aty/ |
H A D | radeon_monitor.c | 224 rinfo->panel_info.clock = BIOS_IN16(tmp0+9); 240 pr_debug(" clock: %d\n", rinfo->panel_info.clock); 691 rinfo->panel_info.clock = 100000000 / var->pixclock; 789 var->pixclock = 100000000 / rinfo->panel_info.clock;
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/drivers/video/exynos/ |
H A D | exynos_dp_core.h | 30 struct clk *clock; member in struct:exynos_dp_device
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/drivers/video/via/ |
H A D | lcd.c | 551 u32 clock; local 565 clock = PICOS2KHZ(panel_crt_table->pixclock) * 1000; 566 plvds_setting_info->vclk = clock; 593 viafb_set_vclock(clock, set_iga);
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/drivers/net/hamradio/ |
H A D | scc.c | 732 set_brg(scc, (unsigned) (scc->clock / (scc->modem.speed * 64)) - 2); 762 * WR11 XXXXXXXX clock control 799 wr(scc,R4,X1CLK|SDLC); /* *1 clock, SDLC mode */ 810 /* set clock sources: 908 time_const = (unsigned) (scc->clock / (scc->modem.speed * (tx? 2:64))) - 2; 1751 if (hwcfg.clock == 0) 1752 hwcfg.clock = SCC_DEFAULT_CLOCK; 1794 SCC_Info[2*Nchips+chan].clock = hwcfg.clock; 2022 /* dev data ctrl irq clock bran [all...] |
/drivers/usb/host/ |
H A D | ehci-sched.c | 2293 unsigned now_uframe, frame, clock, clock_frame, mod; local 2305 clock = ehci_read_frame_index(ehci); 2306 clock_frame = (clock >> 3) & (ehci->periodic_size - 1); 2308 clock = now_uframe + mod - 1; 2315 clock &= mod - 1; 2316 clock_frame = clock >> 3; 2455 now_uframe = clock; 2477 if (now_uframe == clock) { 2489 clock = now; 2490 clock_frame = clock >> [all...] |
/drivers/usb/gadget/ |
H A D | m66592-udc.c | 617 unsigned int clock, vif, irq_sense; local 631 clock = M66592_XTAL12; 634 clock = M66592_XTAL24; 637 clock = M66592_XTAL48; 641 clock = 0; 660 m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, 1214 * When USB clock stops, it cannot read register. Even if a 1215 * clock stops, the interrupt occurs. So this driver turn on 1216 * a clock by this timing and do re-reading of register. 1679 dev_err(&pdev->dev, "cannot get clock \" [all...] |
/drivers/gpu/drm/gma500/ |
H A D | cdv_intel_lvds.c | 308 adjusted_mode->clock = panel_fixed_mode->clock;
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H A D | oaktrail_hdmi.c | 183 if (mode->clock > 165000) 185 if (mode->clock < 20000)
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H A D | psb_drv.c | 521 mode->clock = umode->clock;
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H A D | psb_intel_lvds.c | 429 adjusted_mode->clock = panel_fixed_mode->clock;
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