Searched refs:clock (Results 26 - 50 of 324) sorted by relevance

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/drivers/gpu/drm/gma500/
H A Dmdfld_tpo_vid.c60 mode->clock = ti->pixel_clock * 10;
70 dev_dbg(dev->dev, "clock is %d\n", mode->clock);
80 mode->clock = 33264;
H A Dmdfld_intel_display.c720 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
721 static void mdfld_clock(int refclk, struct mrst_clock_t *clock) argument
723 clock->dot = (refclk * clock->m) / clock->p1;
727 * Returns a set of divisors for the desired target clock with the given refclk,
734 struct mrst_clock_t clock; local
740 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock
785 struct mrst_clock_t clock; local
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H A Dmdfld_tmd_vid.c63 mode->clock = ti->pixel_clock * 10;
73 dev_dbg(dev->dev, "clock is %d\n", mode->clock);
83 mode->clock = 33264;
/drivers/i2c/algos/
H A Di2c-algo-pca.c396 int clock; local
426 "%s: Invalid I2C clock speed selected."
432 "Choosing the clock frequency based on "
439 clock = pca_clock(pca_data);
441 adap->name, freqs[clock]);
443 pca_set_con(pca_data, I2C_PCA_CON_ENSIO | clock);
445 int clock; local
452 * They are used (added) below to calculate the clock dividers
455 * maximum clock rate for each mode
465 printk(KERN_WARNING "%s: I2C clock spee
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/drivers/gpu/drm/radeon/
H A Dradeon_clocks.c37 struct radeon_pll *spll = &rdev->clock.spll;
67 struct radeon_pll *mpll = &rdev->clock.mpll;
96 * Read XTAL (ref clock), SCLK and MCLK from Open Firmware device
104 struct radeon_pll *p1pll = &rdev->clock.p1pll;
105 struct radeon_pll *p2pll = &rdev->clock.p2pll;
106 struct radeon_pll *spll = &rdev->clock.spll;
107 struct radeon_pll *mpll = &rdev->clock.mpll;
143 rdev->clock.max_pixel_clock = 35000;
152 rdev->clock.default_sclk = (*val) / 10;
154 rdev->clock
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/drivers/gpu/drm/i915/
H A Dintel_display.c82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
449 static void pineview_clock(int refclk, intel_clock_t *clock) argument
451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock
457 intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock) argument
491 intel_PLL_is_valid(struct drm_device *dev, const intel_limit_t *limit, const intel_clock_t *clock) argument
528 intel_clock_t clock; local
594 intel_clock_t clock; local
661 intel_clock_t clock; local
687 intel_clock_t clock; local
2349 ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) argument
3978 int clock = crtc->mode.clock; local
4039 int htotal, hdisplay, clock, pixel_size; local
4123 int hdisplay, htotal, pixel_size, clock; local
4226 int clock = crtc->mode.clock; local
4339 int clock = enabled->mode.clock; local
4474 int hdisplay, htotal, pixel_size, clock; local
4725 int clock; local
4758 int clock; local
5090 i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode, intel_clock_t *clock) argument
5112 i9xx_update_pll_dividers(struct drm_crtc *crtc, intel_clock_t *clock, intel_clock_t *reduced_clock) argument
5158 intel_clock_t clock, reduced_clock; local
5667 intel_clock_t clock, reduced_clock; local
6883 intel_clock_t clock; local
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/drivers/i2c/busses/
H A Di2c-pca-isa.c44 * in the actual clock rate */
45 static int clock = 59000; variable
160 pca_isa_data.i2c_clock = clock;
219 module_param(clock, int, 0);
220 MODULE_PARM_DESC(clock, "Clock rate in hertz.\n\t\t"
H A Di2c-mpc.c76 u32 clock, u32 prescaler);
97 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
196 static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock, argument
204 if (clock == MPC_I2C_CLOCK_LEGACY) {
211 divider = mpc5xxx_get_bus_frequency(node) / clock;
232 u32 clock, u32 prescaler)
236 if (clock == MPC_I2C_CLOCK_PRESERVE) {
242 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
248 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
254 u32 clock, u3
230 mpc_i2c_setup_52xx(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) argument
252 mpc_i2c_setup_52xx(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) argument
260 mpc_i2c_setup_512x(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) argument
288 mpc_i2c_setup_512x(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) argument
345 mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock, u32 prescaler, u32 *real_clk) argument
383 mpc_i2c_setup_8xxx(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) argument
408 mpc_i2c_setup_8xxx(struct device_node *node, struct mpc_i2c *i2c, u32 clock, u32 prescaler) argument
604 u32 clock = MPC_I2C_CLOCK_LEGACY; local
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H A Di2c-pmcmsp.c84 /* Corresponds to a PMCTWI clock configuration register */
87 u16 clock; /* Bits 9:0, default = 0x001f */ member in struct:pmcmsptwi_clock
91 struct pmcmsptwi_clock standard; /* The standard/fast clock config */
92 struct pmcmsptwi_clock highspeed; /* The highspeed clock config */
128 .clock = 0x1f,
132 .clock = 0x1f,
151 const struct pmcmsptwi_clock *clock)
153 return ((clock->filter & 0xf) << 12) | (clock->clock
150 pmcmsptwi_clock_to_reg( const struct pmcmsptwi_clock *clock) argument
156 pmcmsptwi_reg_to_clock( u32 reg, struct pmcmsptwi_clock *clock) argument
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/drivers/isdn/mISDN/
H A DMakefile11 mISDN_core-objs := core.o fsm.o socket.o clock.o hwchannel.o stack.o layer1.o layer2.o tei.o timerdev.o
/drivers/media/dvb/frontends/
H A Daf9013.h45 * clock
48 u32 clock; member in struct:af9013_config
/drivers/media/video/s5p-fimc/
H A Dmipi-csis.c104 * @clock: CSIS clocks
117 struct clk *clock[NUM_CSIS_CLOCKS]; member in struct:csis_state
246 /* Not using external clock. */
260 if (IS_ERR_OR_NULL(state->clock[i]))
262 clk_unprepare(state->clock[i]);
263 clk_put(state->clock[i]);
264 state->clock[i] = NULL;
274 state->clock[i] = clk_get(dev, csi_clock_name[i]);
275 if (IS_ERR(state->clock[i]))
277 ret = clk_prepare(state->clock[
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/drivers/net/wireless/prism54/
H A Dislpci_eth.h28 __le32 clock; /* 1MHz clock */ member in struct:rfmon_header
/drivers/ptp/
H A Dptp_chardev.c2 * PTP 1588 clock support - character device implementation.
21 #include <linux/posix-clock.h>
36 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
100 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
110 struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
/drivers/video/via/
H A Dvia_clock.h23 * clock and PLL management functions
74 void via_clock_init(struct via_clock *clock, int gfx_chip);
/drivers/media/video/uvc/
H A Duvc_video.c417 if (dev_sof == stream->clock.last_sof)
420 stream->clock.last_sof = dev_sof;
444 if (stream->clock.sof_offset == (u16)-1) {
447 stream->clock.sof_offset = delta_sof;
449 stream->clock.sof_offset = 0;
452 dev_sof = (dev_sof + stream->clock.sof_offset) & 2047;
454 spin_lock_irqsave(&stream->clock.lock, flags);
456 sample = &stream->clock.samples[stream->clock.head];
463 stream->clock
473 struct uvc_clock *clock = &stream->clock; local
483 struct uvc_clock *clock = &stream->clock; local
596 struct uvc_clock *clock = &stream->clock; local
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/drivers/video/exynos/
H A Dexynos_mipi_dsi.c126 clk_disable(dsim->clock);
161 clk_enable(dsim->clock);
371 dsim->clock = clk_get(&pdev->dev, "dsim0");
372 if (IS_ERR(dsim->clock)) {
373 dev_err(&pdev->dev, "failed to get dsim clock source\n");
377 clk_enable(dsim->clock);
475 clk_disable(dsim->clock);
476 clk_put(dsim->clock);
492 clk_disable(dsim->clock);
493 clk_put(dsim->clock);
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/drivers/mfd/
H A Dsm501.c131 * Print out the current clock configuration for the device
321 unsigned long clock; local
327 clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK);
360 smc501_writel(clock, sm->regs + SM501_POWER_MODE_0_CLOCK);
366 smc501_writel(clock, sm->regs + SM501_POWER_MODE_1_CLOCK);
378 dev_dbg(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
379 gate, clock, mode);
390 /* clock value structure. */
400 * Calculates the nearest discrete clock frequency that
401 * can be achieved with the specified input clock
405 sm501_calc_clock(unsigned long freq, struct sm501_clock *clock, int max_div, unsigned long mclk, long *best_diff) argument
449 sm501_calc_pll(unsigned long freq, struct sm501_clock *clock, int max_div) argument
487 sm501_select_clock(unsigned long freq, struct sm501_clock *clock, int max_div) argument
516 unsigned long clock = smc501_readl(sm->regs + SM501_CURRENT_CLOCK); local
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/drivers/net/wireless/ath/ath5k/
H A Dreset.c41 * that don't fit on other places such as clock, sleep and power control
89 * ath5k_hw_htoclock() - Translate usec to hw clock units
93 * Translate usecs to hw clock units based on the current
94 * hw clock rate.
96 * Returns number of clock units
106 * ath5k_hw_clocktoh() - Translate hw clock units to usec
108 * @clock: value in hw clock units
110 * Translate hw clock units to usecs based on the current
111 * hw clock rat
116 ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock) argument
134 u32 usec_reg, txlat, rxlat, usec, clock, sclock, txf2txs; local
670 u32 turbo, mode, clock, bus_flags; local
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/drivers/usb/gadget/
H A Dr8a66597-udc.h244 u16 clock = 0; local
248 clock = XTAL12;
251 clock = XTAL24;
254 clock = XTAL48;
257 printk(KERN_ERR "r8a66597: platdata clock is wrong.\n");
261 return clock;
/drivers/video/matrox/
H A Di2c-matroxfb.c78 matroxfb_i2c_set(b->minfo, b->mask.clock, state);
88 return (matroxfb_read_gpio(b->minfo) & b->mask.clock) ? 1 : 0;
102 unsigned int data, unsigned int clock, const char *name,
109 b->mask.clock = clock;
101 i2c_bus_reg(struct i2c_bit_adapter* b, struct matrox_fb_info* minfo, unsigned int data, unsigned int clock, const char *name, int class) argument
/drivers/video/vermilion/
H A Dvermilion.c578 static int vml_nearest_clock(int clock) argument
587 cur_diff = clock - vml_clocks[0];
590 diff = clock - vml_clocks[i];
606 int clock; local
611 clock = PICOS2KHZ(var->pixclock);
614 nearest_clock = subsys->nearest_clock(subsys, clock);
616 nearest_clock = vml_nearest_clock(clock);
623 clock_diff = nearest_clock - clock;
625 if (clock_diff > clock / 5) {
627 printk(KERN_DEBUG MODULE_NAME ": Diff failure. %d %d\n",clock_diff,clock);
787 int clock; local
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/drivers/cpufreq/
H A Delanfreq.c38 int clock; /* frequency in kHz */ member in struct:s_elan_multiplier
92 /* Are we in CPU clock multiplied mode (66/99 MHz)? */
125 freqs.new = elan_multiplier[state].clock;
131 elan_multiplier[state].clock);
154 /* now, set the CPU clock speed register (0x80) */
/drivers/mmc/host/
H A Dsdhci-s3c.c43 * @cur_clk: The index of the current bus clock.
44 * @clk_io: The clock for the internal bus interface.
45 * @clk_bus: The clocks that are available for the SD/MMC bus clock.
78 * get_curclk - convert ctrl2 register to clock source number
95 dev_dbg(&ourhost->pdev->dev, "restored ctrl2 clock setting\n");
104 * sdhci_s3c_get_max_clk - callback to get maximum clock frequency.
107 * Callback to return the maximum clock rate acheivable by the controller.
116 /* note, a reset will reset the clock source */
136 * @src: The source clock index.
137 * @wanted: The clock frequenc
180 sdhci_s3c_set_clock(struct sdhci_host *host, unsigned int clock) argument
288 sdhci_cmu_set_clock(struct sdhci_host *host, unsigned int clock) argument
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/drivers/gpu/drm/
H A Ddrm_modes.c54 mode->base.id, mode->name, mode->vrefresh, mode->clock,
260 /* 15/13. Find pixel clock frequency (kHz for xf86) */
261 drm_mode->clock = drm_mode->htotal * HV_FACTOR * 1000 / hperiod;
262 drm_mode->clock -= drm_mode->clock % CVT_CLOCK_STEP;
426 /* 21.Find pixel clock frequency: */
451 drm_mode->clock = pixel_freq;
607 calc_val = (mode->clock * 1000) / mode->htotal; /* hsync in Hz */
642 calc_val = (mode->clock * 1000);
777 /* do clock chec
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