Searched refs:control (Results 226 - 250 of 443) sorted by relevance

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/drivers/mfd/
H A Dsm501.c45 void __iomem *control; /* address of control reg. */ member in struct:sm501_gpio_chip
251 * alters the miscellaneous control parameters
911 if (smc501_readl(smchip->control) & bit) {
915 ctrl = smc501_readl(smchip->control);
917 smc501_writel(ctrl, smchip->control);
1031 chip->control = sm->regs + SM501_GPIO63_32_CONTROL;
1035 chip->control = sm->regs + SM501_GPIO31_0_CONTROL;
/drivers/net/wireless/rtlwifi/
H A Dbase.c429 /* <2> rate control register */
488 u8 rate_flag = info->control.rates[0].flags;
507 u8 rate_flag = info->control.rates[0].flags;
543 u8 rate_flag = info->control.rates[0].flags;
857 if (info->control.rates[0].idx == 0 ||
1343 info->control.rates[0].idx = 0;
1344 info->control.sta = sta;
H A Drc.c52 *will control rate at all it just used for
139 struct ieee80211_tx_rate *rates = tx_info->control.rates;
/drivers/tty/serial/
H A Dzs.c142 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; local
146 writeb(reg & 0xf, control);
150 retval = readb(control);
157 void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET; local
160 writeb(reg & 0xf, control);
163 writeb(value, control);
/drivers/acpi/acpica/
H A Ddswexec.c156 * the control stack
206 * DESCRIPTION: Descending callback used during the execution of control
275 walk_state->control_state->control.predicate_op = op;
350 * DESCRIPTION: Ascending callback used during the execution of control
537 * Since the operands will be passed to another control method,
719 (walk_state->control_state->control.predicate_op == op)) {
/drivers/auxdisplay/
H A DKconfig59 int "Delay between each control writing (microseconds)"
63 Amount of time the ks0108 should wait between each control write
/drivers/block/
H A Dnvme.c545 u16 control; local
568 control = 0;
570 control |= NVME_RW_FUA;
572 control |= NVME_RW_LR;
600 cmnd->rw.control = cpu_to_le16(control);
1123 c.rw.control = cpu_to_le16(io.control);
/drivers/char/ipmi/
H A Dipmi_smic_sm.c219 unsigned char control)
221 smic->io->outputb(smic->io, 1, control);
318 /* these are the control/status codes we actually use
218 write_smic_control(struct si_sm_data *smic, unsigned char control) argument
/drivers/gpu/drm/
H A Ddrm_pci.c346 ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL);
381 drm_put_minor(&dev->control);
H A Ddrm_stub.c488 drm_put_minor(&dev->control);
508 drm_unplug_minor(dev->control);
/drivers/net/wan/
H A Dhdlc_cisco.c37 u8 control; member in struct:hdlc_header
89 data->control = 0;
182 netdev_info(dev, "Invalid length of Cisco control packet (%d bytes)\n",
H A Dhdlc_ppp.c54 u8 control; member in struct:hdlc_header
149 data->control != HDLC_CTRL_UI)
180 data->control = HDLC_CTRL_UI;
400 case LCP_OPTION_ACCM: /* async control character map */
453 hdr->control != HDLC_CTRL_UI)
/drivers/scsi/megaraid/
H A Dmegaraid_sas_fusion.c1161 u8 opcode = 0, flagvals = 0, groupnum = 0, control = 0; local
1224 control = cdb[15];
1229 control = cdb[11];
1237 cdb[9] = control;
1250 control = cdb[5];
1257 control = cdb[9];
1264 control = cdb[11];
1273 cdb[15] = control;
/drivers/tty/
H A Damiserial.c108 int MCR; /* Modem control register */
733 /* CTS flow control flag and modem status interrupts */
1154 unsigned char control, status; local
1162 control = info->MCR;
1166 return ((control & SER_RTS) ? TIOCM_RTS : 0)
1167 | ((control & SER_DTR) ? TIOCM_DTR : 0)
1466 * control, which is currently the case. Hence, if it ever
1548 char stat_buf[30], control, status; local
1555 control = (state->tport.flags & ASYNC_INITIALIZED) ? state->MCR : status;
1560 if(!(control
[all...]
/drivers/usb/otg/
H A DKconfig35 optionally control of a D+ pullup GPIO as well as a VBUS
/drivers/pci/
H A Dpci.c2987 u16 control; local
2991 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &control);
2992 control &= ~PCI_MSI_FLAGS_ENABLE;
2993 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, control);
2997 pci_read_config_word(dev, pos + PCI_MSIX_FLAGS, &control);
2998 control &= ~PCI_MSIX_FLAGS_ENABLE;
2999 pci_write_config_word(dev, pos + PCI_MSIX_FLAGS, control);
3021 u16 status, control; local
3048 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &control);
3049 control |
[all...]
/drivers/net/ethernet/atheros/atlx/
H A Datl1.c329 u32 control; local
336 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
337 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
342 control = ioread32(hw->hw_addr + REG_VPD_CAP);
343 if (control & VPD_CAP_VPD_FLAG)
346 if (control & VPD_CAP_VPD_FLAG) {
438 u32 i, control; local
455 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
458 addr[0] = control;
460 addr[1] = control;
[all...]
/drivers/usb/misc/
H A Dftdi-elan.c2300 u32 control; local
2315 retval = ftdi_read_pcimem(ftdi, control, &control);
2329 retval = ftdi_read_pcimem(ftdi, control, &hc_control);
2348 retval = ftdi_write_pcimem(ftdi, control, hc_control);
2351 retval = ftdi_read_pcimem(ftdi, control, &control);
2366 retval = ftdi_read_pcimem(ftdi, control, &control);
2391 retval = ftdi_write_pcimem(ftdi, control, hc_contro
[all...]
/drivers/media/video/
H A Dmt9m111.c127 * Camera control register addresses (0x200..0x2ff not implemented)
151 u16 control; member in struct:mt9m111_context
163 .control = MT9M111_CTXT_CTRL_RESTART,
175 .control = MT9M111_CTXT_CTRL_RESTART |
316 return reg_write(CONTEXT_CONTROL, ctx->control);
/drivers/net/wireless/b43/
H A Ddma.h70 __le32 control; member in struct:b43_dmadesc32
/drivers/net/wireless/zd1211rw/
H A Dzd_mac.h32 u8 control; member in struct:zd_ctrlset
88 /* zd_ctrlset control field */
211 /* whether to pass control frames to stack */
/drivers/scsi/isci/
H A Dphy.c108 tl_control = readl(&iphy->transport_layer_registers->control);
110 writel(tl_control, &iphy->transport_layer_registers->control);
419 tl_control = readl(&iphy->transport_layer_registers->control);
421 writel(tl_control, &iphy->transport_layer_registers->control);
1361 * @func: This parameter specifies the phy control function being invoked.
/drivers/staging/ft1000/
H A Dft1000.h140 #define DSP_RESET_BIT 0x0001 /* Bit field to control dsp reset state */
142 #define ASIC_RESET_BIT 0x0002 /* Bit field to control ASIC reset state */
209 unsigned char control; /* not used */ member in struct:pseudo_hdr
/drivers/staging/ozwpan/
H A Dozpd.c406 f->hdr.control =
511 (((u16)f->hdr.control)<<8)|f->hdr.last_pkt_num,
573 oz_hdr->control = (OZ_PROTOCOL_VERSION<<OZ_VERSION_SHIFT) | OZ_F_ISOC;
749 oz.control =
H A Dozprotocol.h46 u8 control; member in struct:oz_hdr
52 /* Bits in the control field. */

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