Searched refs:BIT_0 (Results 1 - 20 of 20) sorted by relevance
/drivers/scsi/qla2xxx/ |
H A D | qla_fw.h | 18 #define FO1_ENABLE_8016 BIT_0 27 #define PDO_FORCE_PLOGI BIT_0 406 #define CF_WRITE_DATA BIT_0 448 #define TMF_WRITE_DATA BIT_0 526 #define SF_FCP_RSP_DMA BIT_0 814 #define TCF_CLEAR_ACA BIT_0 837 #define AOF_NO_ABTS BIT_0 /* Do not send any ABTS. */ 931 #define CSRX_ISP_SOFT_RESET BIT_0 /* ISP soft reset. */ 1000 #define GPDX_DATA_INOUT (BIT_1|BIT_0) 1008 #define GPEX_ENABLE (BIT_1|BIT_0) [all...] |
H A D | qla_def.h | 59 #define BIT_0 0x1 macro 215 #define SRB_DMA_VALID BIT_0 /* Command sent to ISP */ 231 #define SRB_LOGIN_RETRIED BIT_0 311 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */ 329 #define NVR_CLOCK BIT_0 515 #define MBX_DMA_IN BIT_0 601 #define FO1_AE_ON_LIPF8 BIT_0 615 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 618 #define FO3_ENABLE_EMERG_IOCB BIT_0 763 #define MBX_0 BIT_0 [all...] |
H A D | qla_init.c | 1576 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 1580 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 1590 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 1591 (tx_sens & (BIT_1 | BIT_0)); 1596 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 1598 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 1608 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 1609 (tx_sens & (BIT_1 | BIT_0)); 1638 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 2267 nv->firmware_options[1] |= (BIT_5 | BIT_0); [all...] |
H A D | qla_mbx.c | 123 if (mboxes & BIT_0) 253 if (mboxes & BIT_0) 433 #define EXTENDED_BB_CREDITS BIT_0 1191 mcp->mb[1] = BIT_0; 1665 if (opt & BIT_0) 1728 mb[1] = BIT_0; 1733 mb[10] |= BIT_0; /* Class 2. */ 2257 * BIT_0 = mem alloc error. 2602 mcp->mb[1] = BIT_0; 2880 mcp->mb[2] = BIT_0; [all...] |
H A D | qla_isr.c | 78 if (RD_REG_WORD(®->semaphore) & BIT_0) { 266 if ((cnt == 4 || cnt == 5) && (mboxes & BIT_0)) 268 else if (mboxes & BIT_0) 946 if (le16_to_cpu(mbx->mb1) & BIT_0) 1955 if (mboxes & BIT_0) 2059 for (cnt = 10000; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 && 2071 for (cnt = 100; (RD_REG_DWORD(®->iobase_window) & BIT_0) == 0 &&
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H A D | qla_mid.c | 553 req->options |= BIT_0; 568 rsp->options |= BIT_0;
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H A D | qla_nx.h | 853 #define HINT_MBX_INT_PENDING BIT_0 862 #define ISRX_NX_RISC_INT BIT_0 /* RISC interrupt. */
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H A D | qla_iocb.c | 1620 #define QDSS_GOT_Q_SPACE BIT_0 1914 opts = lio->u.logio.flags & SRB_LOGIN_COND_PLOGI ? BIT_0 : 0; 1978 mbx->mb10 = cpu_to_le16(BIT_0); 1980 mbx->mb1 = cpu_to_le16((sp->fcport->loop_id << 8) | BIT_0);
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H A D | qla_sup.c | 40 while ((data & BIT_0) == 0) { 129 data |= BIT_0; 1071 if ((flags & BIT_0) == 0) 1145 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
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H A D | qla_dbg.c | 786 (RD_REG_WORD(®->mctr) & (BIT_1 | BIT_0)) != 0))) { 824 if (RD_REG_WORD(®->semaphore) & BIT_0) {
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H A D | qla_gs.c | 1132 0xfa, mb, BIT_1|BIT_0);
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H A D | qla_os.c | 476 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
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/drivers/scsi/ |
H A D | qla1280.h | 26 #define BIT_0 0x1 macro 129 #define ISP_CFG0_1020 BIT_0 /* ISP1020 */ 141 #define ISP_CFG1_SXP BIT_0 /* SXP register select */ 143 #define ISP_RESET BIT_0 /* ISP soft reset */ 155 #define NV_CLOCK BIT_0 169 #define CDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ 186 #define DDMA_CONF_DIR BIT_0 /* DMA direction (0=fifo->host 1=host->fifo) */ 212 #define BIOS_ENABLE BIT_0 574 #define RF_CONT BIT_0 /* Continuation. */
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H A D | qla1280.c | 1159 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0; 1233 (ha->bus_settings[bus].qtag_enables & (BIT_0 << target))) { 1736 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb); 1808 BIT_1 | BIT_0, mb); 1825 BIT_1 | BIT_0, mb); 1870 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb); 1880 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]); 1947 BIT_3 | BIT_2 | BIT_1 | BIT_0, 1961 BIT_3 | BIT_2 | BIT_1 | BIT_0, 2135 flag = (BIT_0 << targe [all...] |
/drivers/net/ethernet/qlogic/qlcnic/ |
H A D | qlcnic_ctx.c | 1044 arg1 = (adapter->npars[pci_func].phy_port & BIT_0); 1055 arg2 |= (BIT_0 | BIT_1); 1065 arg2 &= ~BIT_0; 1066 if (!(esw_cfg->offload_flags & BIT_0))
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H A D | qlcnic_hdr.h | 194 #define BIT_0 0x1 macro 497 #define TA_CTL_START BIT_0
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H A D | qlcnic_main.c | 812 if (esw_cfg->offload_flags & BIT_0) { 887 esw_cfg.offload_flags = BIT_0; 888 esw_cfg.mac_override = BIT_0; 889 esw_cfg.promisc_mode = BIT_0; 2021 if (*(skb->data) & BIT_0) { 2022 flags |= BIT_0;
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H A D | qlcnic.h | 1338 #define QLCNIC_DUMP_WCRB BIT_0
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/drivers/scsi/qla4xxx/ |
H A D | ql4_fw.h | 55 #define HINT_MBX_INT_PENDING BIT_0 61 #define HSRX_RISC_MB_INT BIT_0 /* RISC to Host Mailbox interrupt */ 65 #define ISRX_82XX_RISC_INT BIT_0 /* RISC interrupt. */
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H A D | ql4_def.h | 71 #define BIT_0 0x1 macro
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