Searched refs:BIT_1 (Results 1 - 18 of 18) sorted by relevance

/drivers/scsi/qla2xxx/
H A Dqla_fw.h26 #define PDO_FORCE_ADISC BIT_1
38 #define PDF_HARD_ADDR BIT_1
405 #define CF_READ_DATA BIT_1
447 #define TMF_READ_DATA BIT_1
813 #define TCF_TARGET_RESET BIT_1
930 #define CSRX_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable. */
1000 #define GPDX_DATA_INOUT (BIT_1|BIT_0)
1008 #define GPEX_ENABLE (BIT_1|BIT_0)
1117 #define MDBS_ID_ACQUIRED BIT_1
1180 #define CS_VF_SET_QOS_OF_VPORTS BIT_1
[all...]
H A Dqla_def.h60 #define BIT_1 0x2 macro
232 #define SRB_LOGIN_COND_PLOGI BIT_1
310 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
328 #define NVR_SELECT BIT_1
516 #define MBX_DMA_OUT BIT_1
602 #define FO1_AE_ALL_LIP_RESET BIT_1
616 #define FO2_REV_LOOPBACK BIT_1
619 #define FO3_AE_RND_ERROR BIT_1
762 #define MBX_1 BIT_1
852 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
[all...]
H A Dqla_init.c1576 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1580 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1590 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1591 (tx_sens & (BIT_1 | BIT_0));
1596 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
1598 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1608 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
1609 (tx_sens & (BIT_1 | BIT_0));
1813 mid_init_cb->options = __constant_cpu_to_le16(BIT_1);
2202 nv->firmware_options[0] = BIT_2 | BIT_1;
[all...]
H A Dqla_mbx.c1535 mcp->mb[1] = BIT_1;
1667 if (opt & BIT_1)
1726 mb[1] |= BIT_1;
1735 mb[10] |= BIT_1; /* Class 3. */
2258 * BIT_1 = mailbox error.
2882 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
2884 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
3172 rval = BIT_1;
3175 rval = BIT_1;
4166 mcp->mb[2] = BIT_1;
[all...]
H A Dqla_gs.c559 ct_req->req.rff_id.fc4_feature = BIT_1;
1132 0xfa, mb, BIT_1|BIT_0);
H A Dqla_os.c404 options |= BIT_1;
476 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
3590 opts |= BIT_1;
H A Dqla_iocb.c1915 opts |= lio->u.logio.flags & SRB_LOGIN_SKIP_PRLI ? BIT_1 : 0;
H A Dqla_isr.c948 else if (le16_to_cpu(mbx->mb1) & BIT_1)
H A Dqla_dbg.c786 (RD_REG_WORD(&reg->mctr) & (BIT_1 | BIT_0)) != 0))) {
/drivers/scsi/
H A Dqla1280.h27 #define BIT_1 0x2 macro
130 #define ISP_CFG0_1020A BIT_1 /* ISP1020A */
144 #define ISP_EN_INT BIT_1 /* ISP enable interrupts. */
151 #define PCI_INT BIT_1 /* PCI interrupt */
156 #define NV_SELECT BIT_1
168 #define CDMA_CONF_BENAB BIT_1 /* Bus burst enable */
185 #define DDMA_CONF_BENAB BIT_1 /* Bus burst enable */
575 #define RF_FULL BIT_1 /* Full */
973 #define OF_ENABLE_TAG BIT_1 /* Tagged queue action enable */
H A Dqla1280.c1159 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;
1736 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
1808 BIT_1 | BIT_0, mb);
1825 BIT_1 | BIT_0, mb);
1870 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
1880 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
1947 BIT_3 | BIT_2 | BIT_1 | BIT_0,
1961 BIT_3 | BIT_2 | BIT_1 | BIT_0,
2181 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2255 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_
[all...]
/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic.h826 #define QLCNIC_FW_CAPABILITY_TSO BIT_1
1118 #define QLCNIC_SWITCH_ENABLE BIT_1
1339 #define QLCNIC_DUMP_RWCRB BIT_1
H A Dqlcnic_ctx.c1055 arg2 |= (BIT_0 | BIT_1);
1067 arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
1068 if (!(esw_cfg->offload_flags & BIT_1))
H A Dqlcnic_hdr.h195 #define BIT_1 0x2 macro
498 #define TA_CTL_ENABLE BIT_1
H A Dqlcnic_main.c814 if (!(esw_cfg->offload_flags & BIT_1))
891 esw_cfg.offload_flags |= (BIT_1 | BIT_2);
/drivers/scsi/qla4xxx/
H A Dql4_def.h72 #define BIT_1 0x2 macro
H A Dql4_fw.h62 #define HSRX_RISC_IOCB_INT BIT_1 /* RISC to Host IOCB interrupt */
H A Dql4_os.c5077 if (PCI_FUNC(ha->pdev->devfn) & BIT_1)

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