Searched refs:BIT_2 (Results 1 - 12 of 12) sorted by relevance

/drivers/scsi/
H A Dqla1280.h28 #define BIT_2 0x4 macro
131 #define ISP_CFG0_1040 BIT_2 /* ISP1040 */
140 #define ISP_CFG1_BENAB BIT_2 /* Global Bus burst enable */
145 #define ISP_EN_RISC BIT_2 /* ISP enable RISC interrupts. */
150 #define RISC_INT BIT_2 /* RISC interrupt */
157 #define NV_DATA_OUT BIT_2
167 #define CDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
184 #define DDMA_CONF_RIRQ BIT_2 /* RISC interrupt enable */
332 #define NV_START_BIT BIT_2
576 #define RF_BAD_HEADER BIT_2 /* Ba
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H A Dqla1280.c1159 mr = BIT_3 | BIT_2 | BIT_1 | BIT_0;
1736 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
1807 err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 |
1824 err = qla1280_mailbox_command(ha, BIT_4 | BIT_3 | BIT_2 |
1947 BIT_3 | BIT_2 | BIT_1 | BIT_0,
1961 BIT_3 | BIT_2 | BIT_1 | BIT_0,
2255 BIT_7 | BIT_3 | BIT_2 | BIT_1 | BIT_0);
2296 status |= qla1280_mailbox_command(ha, BIT_7 | BIT_6 | BIT_2 |
2303 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2317 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_
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/drivers/scsi/qla2xxx/
H A Dqla_fw.h404 #define CF_DATA_SEG_DESCR_ENABLE BIT_2
446 #define TMF_DSD_LIST_ENABLE BIT_2
812 #define TCF_CLEAR_TASK_SET BIT_2
929 #define CSRX_64BIT_SLOT BIT_2 /* PCI 64-Bit Bus Slot. */
992 #define GPDX_LED_COLOR_MASK (BIT_4|BIT_3|BIT_2)
996 #define GPDX_LED_YELLOW_ON BIT_2
1181 #define CS_VF_SET_HOPS_OF_VPORTS BIT_2
1375 #define FSTATE_IS_DIAG_FW BIT_2
1391 #define VCO_DONT_RESET_UPDATE BIT_2
H A Dqla_def.h61 #define BIT_2 0x4 macro
217 #define SRB_CRC_CTX_DMA_VALID BIT_2 /* DIF: context DMA valid */
233 #define SRB_LOGIN_SKIP_PRLI BIT_2
327 #define NVR_DATA_OUT BIT_2
517 #define IOCTL_CMD BIT_2
761 #define MBX_2 BIT_2
852 #define QLA_ZIO_MODE_6 (BIT_2 | BIT_1)
983 #define NV_START_BIT BIT_2
1274 #define CF_ORDERED_TAG BIT_2
1448 #define RF_INV_E_TYPE BIT_2 /* Invali
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H A Dqla_init.c1454 (ha->fw_attributes & BIT_2)) {
1572 if (ha->fw_seriallink_options[3] & BIT_2) {
1576 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
1580 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
1598 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
2202 nv->firmware_options[0] = BIT_2 | BIT_1;
2209 nv->firmware_options[0] = BIT_2 | BIT_1;
2236 nv->host_p[1] = BIT_2;
2271 nv->firmware_options[0] |= BIT_2;
2287 nv->firmware_options[0] |= BIT_2;
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H A Dqla_os.c476 lspeed = pcie_lstat & (BIT_0 | BIT_1 | BIT_2 | BIT_3);
500 if (pci_bus & BIT_2)
505 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
H A Dqla_mbx.c2882 mcp->mb[3] = port_speed & (BIT_5|BIT_4|BIT_3|BIT_2|BIT_1|BIT_0);
2884 mcp->mb[3] = port_speed & (BIT_2|BIT_1|BIT_0);
4168 mcp->mb[2] = BIT_2;
/drivers/net/ethernet/qlogic/qlcnic/
H A Dqlcnic_ctx.c1051 arg1 &= ~(BIT_2 | BIT_3);
1057 arg2 |= (BIT_2 | BIT_3);
1067 arg2 &= ~(BIT_1 | BIT_2 | BIT_3);
1069 arg2 &= ~BIT_2;
1070 if (!(esw_cfg->offload_flags & BIT_2))
1074 arg1 |= (BIT_2 | BIT_5);
H A Dqlcnic_hdr.h196 #define BIT_2 0x4 macro
499 #define TA_CTL_WRITE BIT_2
H A Dqlcnic.h1119 #define QLCNIC_SWITCH_VLAN_FILTERING BIT_2
1340 #define QLCNIC_DUMP_ANDCRB BIT_2
H A Dqlcnic_main.c816 if (!(esw_cfg->offload_flags & BIT_2))
891 esw_cfg.offload_flags |= (BIT_1 | BIT_2);
/drivers/scsi/qla4xxx/
H A Dql4_def.h73 #define BIT_2 0x4 macro

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