/drivers/net/ethernet/smsc/ |
H A D | smc9194.h | 139 #define INT_MASK 13 macro 215 mask = inb( ioaddr + INT_MASK );\ 217 outb( mask, ioaddr + INT_MASK ); \ 225 mask = inb( ioaddr + INT_MASK );\ 227 outb( mask, ioaddr + INT_MASK ); \
|
H A D | smc9194.c | 363 outb( 0, ioaddr + INT_MASK ); 383 outb( SMC_INTERRUPT_MASK, ioaddr + INT_MASK ); 404 outb( 0, ioaddr + INT_MASK ); 776 outb( IM_ALLOC_INT, ioaddr + INT_MASK ); 811 outb( 0, ioaddr + INT_MASK ); 1389 mask = inb( ioaddr + INT_MASK ); 1391 outb( 0, ioaddr + INT_MASK ); 1469 outb( mask, ioaddr + INT_MASK );
|
/drivers/watchdog/ |
H A D | sp805_wdt.c | 52 #define INT_MASK (1 << 0) macro 119 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK)) 133 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
|
/drivers/net/wireless/rtl818x/ |
H A D | rtl818x.h | 41 __le16 INT_MASK; member in struct:rtl818x_csr
|
/drivers/net/ethernet/ |
H A D | ethoc.c | 35 #define INT_MASK 0x08 macro 260 u32 imask = ethoc_read(dev, INT_MASK); 262 ethoc_write(dev, INT_MASK, imask); 267 u32 imask = ethoc_read(dev, INT_MASK); 269 ethoc_write(dev, INT_MASK, imask); 554 mask = ethoc_read(priv, INT_MASK);
|
/drivers/net/ethernet/marvell/ |
H A D | pxa168_eth.c | 67 #define INT_MASK 0x0458 macro 670 wrl(pep, INT_MASK, ALL_INTS); 688 wrl(pep, INT_MASK, 0); 921 wrl(pep, INT_MASK, 0); 984 wrl(pep, INT_MASK, 0); 1168 wrl(pep, INT_MASK, 0); 1248 wrl(pep, INT_MASK, ALL_INTS);
|
H A D | mv643xx_eth.c | 135 #define INT_MASK 0x0068 macro 2073 wrlp(mp, INT_MASK, 0); 2190 wrlp(mp, INT_MASK, mp->int_mask); 2376 wrlp(mp, INT_MASK, mp->int_mask); 2422 wrlp(mp, INT_MASK, 0x00000000); 2423 rdlp(mp, INT_MASK); 2514 wrlp(mp, INT_MASK, 0x00000000); 2515 rdlp(mp, INT_MASK); 2519 wrlp(mp, INT_MASK, mp->int_mask); 2993 wrlp(mp, INT_MASK, [all...] |
/drivers/net/tokenring/ |
H A D | 3c359.h | 116 #define INT_MASK 0xFF5 macro
|
H A D | 3c359.c | 745 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 746 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 1180 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ; 1181 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
|
/drivers/gpu/drm/radeon/ |
H A D | evergreen.c | 2558 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2559 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2561 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2562 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2565 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2566 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2717 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2718 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2720 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2721 WREG32(INT_MASK [all...] |
H A D | si.c | 3117 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 3118 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 3120 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 3121 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 3124 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 3125 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 3331 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 3332 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 3334 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 3335 WREG32(INT_MASK [all...] |
H A D | sid.h | 260 #define INT_MASK 0x6b40 macro
|
H A D | evergreend.h | 528 #define INT_MASK 0x6b40 macro
|
/drivers/pci/hotplug/ |
H A D | cpqphp_core.c | 1195 writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_MASK); 1219 writel(0x0L, ctrl->hpc_reg + INT_MASK); 1324 writel(0xFFFFFFC0L | ~rc, ctrl->hpc_reg + INT_MASK);
|
H A D | cpqphp.h | 159 INT_MASK = offsetof(struct ctrl_reg, int_mask), enumerator in enum:ctrl_offsets
|
H A D | cpqphp_ctrl.c | 1223 writel(0, ctrl->hpc_reg + INT_MASK);
|
/drivers/video/msm/ |
H A D | mdp_ppp.c | 211 #define INT_MASK (~FRAC_MASK) macro 259 od_p = od & INT_MASK; 273 oreq = (os_p & INT_MASK) - ONE;
|
/drivers/net/wireless/rtl818x/rtl8180/ |
H A D | dev.c | 352 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); 575 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); 652 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
|
/drivers/net/wireless/rtl818x/rtl8187/ |
H A D | dev.c | 653 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0); 833 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); 961 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF); 1015 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
|
/drivers/net/ethernet/rdc/ |
H A D | r6040.c | 165 #define INT_MASK (RX_INTS | TX_INTS) macro 402 iowrite16(INT_MASK, ioaddr + MIER);
|
/drivers/staging/comedi/drivers/ |
H A D | cb_pcidas.c | 115 #define INT_MASK 0x3 /* mask of interrupt select bits */ macro 1297 devpriv->adc_fifo_bits &= ~INT_MASK;
|
/drivers/i2c/busses/ |
H A D | i2c-bfin-twi.c | 72 DEFINE_TWI_REG(INT_MASK, 0x24)
|
/drivers/mfd/ |
H A D | asic3.c | 401 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
|
/drivers/infiniband/hw/qib/ |
H A D | qib_iba7322.c | 182 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask) macro 867 #define QIB_I_C_ERROR INT_MASK(Err) 870 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail) 871 #define QIB_I_GPIO INT_MASK(AssertGPIO)
|