Searched refs:INT_MASK (Results 1 - 24 of 24) sorted by relevance

/drivers/net/ethernet/smsc/
H A Dsmc9194.h139 #define INT_MASK 13 macro
215 mask = inb( ioaddr + INT_MASK );\
217 outb( mask, ioaddr + INT_MASK ); \
225 mask = inb( ioaddr + INT_MASK );\
227 outb( mask, ioaddr + INT_MASK ); \
H A Dsmc9194.c363 outb( 0, ioaddr + INT_MASK );
383 outb( SMC_INTERRUPT_MASK, ioaddr + INT_MASK );
404 outb( 0, ioaddr + INT_MASK );
776 outb( IM_ALLOC_INT, ioaddr + INT_MASK );
811 outb( 0, ioaddr + INT_MASK );
1389 mask = inb( ioaddr + INT_MASK );
1391 outb( 0, ioaddr + INT_MASK );
1469 outb( mask, ioaddr + INT_MASK );
/drivers/watchdog/
H A Dsp805_wdt.c52 #define INT_MASK (1 << 0) macro
119 if (!(readl_relaxed(wdt->base + WDTRIS) & INT_MASK))
133 writel_relaxed(INT_MASK, wdt->base + WDTINTCLR);
/drivers/net/wireless/rtl818x/
H A Drtl818x.h41 __le16 INT_MASK; member in struct:rtl818x_csr
/drivers/net/ethernet/
H A Dethoc.c35 #define INT_MASK 0x08 macro
260 u32 imask = ethoc_read(dev, INT_MASK);
262 ethoc_write(dev, INT_MASK, imask);
267 u32 imask = ethoc_read(dev, INT_MASK);
269 ethoc_write(dev, INT_MASK, imask);
554 mask = ethoc_read(priv, INT_MASK);
/drivers/net/ethernet/marvell/
H A Dpxa168_eth.c67 #define INT_MASK 0x0458 macro
670 wrl(pep, INT_MASK, ALL_INTS);
688 wrl(pep, INT_MASK, 0);
921 wrl(pep, INT_MASK, 0);
984 wrl(pep, INT_MASK, 0);
1168 wrl(pep, INT_MASK, 0);
1248 wrl(pep, INT_MASK, ALL_INTS);
H A Dmv643xx_eth.c135 #define INT_MASK 0x0068 macro
2073 wrlp(mp, INT_MASK, 0);
2190 wrlp(mp, INT_MASK, mp->int_mask);
2376 wrlp(mp, INT_MASK, mp->int_mask);
2422 wrlp(mp, INT_MASK, 0x00000000);
2423 rdlp(mp, INT_MASK);
2514 wrlp(mp, INT_MASK, 0x00000000);
2515 rdlp(mp, INT_MASK);
2519 wrlp(mp, INT_MASK, mp->int_mask);
2993 wrlp(mp, INT_MASK,
[all...]
/drivers/net/tokenring/
H A D3c359.h116 #define INT_MASK 0xFF5 macro
H A D3c359.c745 writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
746 writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1180 writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
1181 writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
/drivers/gpu/drm/radeon/
H A Devergreen.c2558 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2559 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2561 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2562 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2565 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2566 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2717 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2718 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2720 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2721 WREG32(INT_MASK
[all...]
H A Dsi.c3117 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3118 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3120 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3121 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3124 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3125 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3331 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3332 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3334 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3335 WREG32(INT_MASK
[all...]
H A Dsid.h260 #define INT_MASK 0x6b40 macro
H A Devergreend.h528 #define INT_MASK 0x6b40 macro
/drivers/pci/hotplug/
H A Dcpqphp_core.c1195 writel(0xFFFFFFFFL, ctrl->hpc_reg + INT_MASK);
1219 writel(0x0L, ctrl->hpc_reg + INT_MASK);
1324 writel(0xFFFFFFC0L | ~rc, ctrl->hpc_reg + INT_MASK);
H A Dcpqphp.h159 INT_MASK = offsetof(struct ctrl_reg, int_mask), enumerator in enum:ctrl_offsets
H A Dcpqphp_ctrl.c1223 writel(0, ctrl->hpc_reg + INT_MASK);
/drivers/video/msm/
H A Dmdp_ppp.c211 #define INT_MASK (~FRAC_MASK) macro
259 od_p = od & INT_MASK;
273 oreq = (os_p & INT_MASK) - ONE;
/drivers/net/wireless/rtl818x/rtl8180/
H A Ddev.c352 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
575 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
652 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
/drivers/net/wireless/rtl818x/rtl8187/
H A Ddev.c653 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
833 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
961 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
1015 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
/drivers/net/ethernet/rdc/
H A Dr6040.c165 #define INT_MASK (RX_INTS | TX_INTS) macro
402 iowrite16(INT_MASK, ioaddr + MIER);
/drivers/staging/comedi/drivers/
H A Dcb_pcidas.c115 #define INT_MASK 0x3 /* mask of interrupt select bits */ macro
1297 devpriv->adc_fifo_bits &= ~INT_MASK;
/drivers/i2c/busses/
H A Di2c-bfin-twi.c72 DEFINE_TWI_REG(INT_MASK, 0x24)
/drivers/mfd/
H A Dasic3.c401 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
/drivers/infiniband/hw/qib/
H A Dqib_iba7322.c182 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask) macro
867 #define QIB_I_C_ERROR INT_MASK(Err)
870 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
871 #define QIB_I_GPIO INT_MASK(AssertGPIO)

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