Searched refs:STATUS_REG (Results 1 - 16 of 16) sorted by relevance

/drivers/scsi/
H A DNCR5380.c425 status = NCR5380_read(STATUS_REG);
430 printk("STATUS_REG: %02x ", status);
466 status = NCR5380_read(STATUS_REG);
905 for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) {
912 NCR5380_poll_politely(instance, STATUS_REG, SR_BSY, 0, 5*HZ);
1181 if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) {
1189 } else if ((NCR5380_read(STATUS_REG) & SR_RST) == SR_RST) {
1220 dprintk(NDEBUG_INTR, ("scsi : unknown interrupt, BASR 0x%X, MR 0x%X, SR 0x%x\n", basr, NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG)));
1454 value = NCR5380_read(STATUS_REG) & (SR_BSY | SR_IO);
1466 if ((NCR5380_read(STATUS_REG)
[all...]
H A Datari_NCR5380.c572 status = NCR5380_read(STATUS_REG);
577 printk("STATUS_REG: %02x ", status);
618 status = NCR5380_read(STATUS_REG);
1239 NCR5380_read(STATUS_REG));
1254 if ((NCR5380_read(STATUS_REG) & PHASE_MASK) == p && (p & SR_IO)) {
1297 if ((NCR5380_read(STATUS_REG) & (SR_SEL|SR_IO)) == (SR_SEL|SR_IO)) {
1306 } else if ((NCR5380_read(STATUS_REG) & SR_RST) == SR_RST) {
1338 NCR5380_read(STATUS_REG));
1346 NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG));
1613 !(NCR5380_read(STATUS_REG)
[all...]
H A Dsun3_NCR5380.c520 status = NCR5380_read(STATUS_REG);
525 printk("STATUS_REG: %02x ", status);
565 status = NCR5380_read(STATUS_REG);
1162 NCR5380_read(STATUS_REG));
1227 if ((NCR5380_read(STATUS_REG) & (SR_SEL|SR_IO)) == (SR_SEL|SR_IO)) {
1238 else if ((NCR5380_read(STATUS_REG) & SR_RST) == SR_RST) {
1271 NCR5380_read(STATUS_REG));
1284 NCR5380_read(MODE_REG), NCR5380_read(STATUS_REG));
1557 while (time_before(jiffies, timeout) && !(NCR5380_read(STATUS_REG) &
1560 if ((NCR5380_read(STATUS_REG)
[all...]
H A Dmac_scsi.c343 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
449 && !(NCR5380_read(STATUS_REG) & SR_REQ))
541 && (!(NCR5380_read(STATUS_REG) & SR_REQ)
H A DNCR5380.h122 #define STATUS_REG 4 /* ro */ macro
H A Dsun3_scsi.c348 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
H A Dsun3_scsi_vme.c317 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) ));
H A Dsym53c416.c53 #define STATUS_REG 0x04 /* Status Register (READ) */ macro
338 status_reg = inb(base + STATUS_REG);
533 while(time_before(jiffies, i) && !(inb(base + STATUS_REG) & SCI))
H A Datari_scsi.c836 PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG)));
H A Dg_NCR5380.c878 status = NCR5380_read(STATUS_REG);
/drivers/rtc/
H A Drtc-spear.c30 #define STATUS_REG 0x14 macro
69 /* STATUS_REG */
93 val = readl(config->ioaddr + STATUS_REG);
95 writel(val, config->ioaddr + STATUS_REG);
128 if ((readl(config->ioaddr + STATUS_REG)) & STATUS_FAIL)
143 status = readl(config->ioaddr + STATUS_REG);
159 irq_data = readl(config->ioaddr + STATUS_REG);
/drivers/input/keyboard/
H A Dspear-keyboard.c30 #define STATUS_REG 0x0C /* 2 bit reg */ macro
73 sts = readb(kbd->io_base + STATUS_REG);
93 writeb(0, kbd->io_base + STATUS_REG);
114 writeb(1, kbd->io_base + STATUS_REG);
/drivers/staging/comedi/drivers/
H A Dni_at_a2150.c105 #define STATUS_REG 0x12 /* read only */ macro
220 printk("status bits 0x%x\n", inw(dev->iobase + STATUS_REG));
248 status = inw(dev->iobase + STATUS_REG);
337 int status = inw(dev->iobase + STATUS_REG);
452 if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
777 if (inw(dev->iobase + STATUS_REG) & FNE_BIT)
791 if (inw(dev->iobase + STATUS_REG) & FNE_BIT)
/drivers/net/ethernet/i825xx/
H A Deepro.c393 #define STATUS_REG 0x01 /* Register 1 */ macro
475 #define eepro_clear_int(ioaddr) outb(ALL_MASK, ioaddr + STATUS_REG)
507 #define eepro_ack_rx(ioaddr) outb (RX_INT, ioaddr + STATUS_REG)
510 #define eepro_ack_tx(ioaddr) outb (TX_INT, ioaddr + STATUS_REG)
1205 while (((status = inb(ioaddr + STATUS_REG)) & (RX_INT|TX_INT)) && (boguscount--))
1369 if (inb(ioaddr + STATUS_REG) & 0x08)
1372 outb(0x08, ioaddr + STATUS_REG);
1416 outb(0x00, ioaddr + STATUS_REG);
/drivers/misc/lis3lv02d/
H A Dlis3lv02d.h52 STATUS_REG = 0x27, enumerator in enum:lis3_reg
/drivers/net/ethernet/qlogic/
H A Dqla3xxx.h699 STATUS_REG = 1, enumerator in enum:__anon2830

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