Searched refs:channel_readl (Results 1 - 6 of 6) sorted by relevance
/drivers/dma/ |
H A D | at_hdmac_regs.h | 237 #define channel_readl(atchan, name) \ macro 340 channel_readl(atchan, SADDR), 341 channel_readl(atchan, DADDR), 342 channel_readl(atchan, CTRLA), 343 channel_readl(atchan, CTRLB), 344 channel_readl(atchan, CFG), 345 channel_readl(atchan, DSCR));
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H A D | dw_dmac.c | 204 channel_readl(dwc, SAR), 205 channel_readl(dwc, DAR), 206 channel_readl(dwc, LLP), 207 channel_readl(dwc, CTL_HI), 208 channel_readl(dwc, CTL_LO)); 322 llp = channel_readl(dwc, LLP); 444 return channel_readl(dwc, SAR); 451 return channel_readl(dwc, DAR); 466 channel_readl(dwc, LLP)); 491 channel_readl(dw [all...] |
H A D | dw_dmac_regs.h | 178 #define channel_readl(dwc, name) \ macro
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H A D | at_hdmac.c | 212 channel_readl(atchan, SADDR), 213 channel_readl(atchan, DADDR), 214 channel_readl(atchan, CTRLA), 215 channel_readl(atchan, CTRLB), 216 channel_readl(atchan, DSCR)); 445 channel_readl(atchan, DSCR)); 1477 atchan->save_dscr = channel_readl(atchan, DSCR); 1495 atchan->save_cfg = channel_readl(atchan, CFG);
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H A D | txx9dmac.c | 54 #define channel_readl(dc, name) \ macro 343 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { 642 csr = channel_readl(dc, CSR); 660 channel_readl(dc, CSR)); 687 csr = channel_readl(dc, CSR); 991 if (!(channel_readl(dc, CSR) & TXX9_DMA_CSR_CHNEN) && 1032 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { 1094 BUG_ON(channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT);
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H A D | pch_dma.c | 121 #define channel_readl(pdc, name) \ macro 779 pd->ch_regs[i].dev_addr = channel_readl(pd_chan, DEV_ADDR); 780 pd->ch_regs[i].mem_addr = channel_readl(pd_chan, MEM_ADDR); 781 pd->ch_regs[i].size = channel_readl(pd_chan, SIZE); 782 pd->ch_regs[i].next = channel_readl(pd_chan, NEXT);
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