Searched refs:lane (Results 1 - 15 of 15) sorted by relevance

/drivers/video/exynos/
H A Dexynos_dp_core.c241 int pre_emphasis, int lane)
243 switch (lane) {
264 int lane; local
272 for (lane = 0; lane < lane_count; lane++)
273 dp->link_train.cr_loop[lane] = 0;
290 for (lane = 0; lane < lane_count; lane
240 exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp, int pre_emphasis, int lane) argument
311 exynos_dp_get_lane_status(u8 link_status[6], int lane) argument
321 int lane; local
334 int lane; local
351 exynos_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane) argument
360 exynos_dp_get_adjust_request_pre_emphasis( u8 adjust_request[2], int lane) argument
370 exynos_dp_set_lane_link_training(struct exynos_dp_device *dp, u8 training_lane_set, int lane) argument
391 exynos_dp_get_lane_link_training( struct exynos_dp_device *dp, int lane) argument
434 int lane; local
461 int lane; local
477 int lane; local
564 int lane; local
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H A Dexynos_mipi_dsi_lowlevel.h49 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane,
H A Dexynos_mipi_dsi_lowlevel.c253 void exynos_mipi_dsi_enable_lane(struct mipi_dsim_device *dsim, unsigned int lane, argument
261 reg |= DSIM_LANE_ENx(lane);
263 reg &= ~DSIM_LANE_ENx(lane);
274 /* get the data lane number. */
421 * check clock and data lane states.
/drivers/gpu/drm/radeon/
H A Datombios_dp.c298 int lane)
300 int i = DP_LANE0_1_STATUS + (lane >> 1);
301 int s = (lane & 1) * 4;
309 int lane; local
312 for (lane = 0; lane < lane_count; lane++) {
313 lane_status = dp_get_lane_status(link_status, lane);
325 int lane; local
331 for (lane
297 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument
339 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument
352 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], int lane) argument
373 int lane; local
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/drivers/net/ethernet/sfc/
H A Dtxc43128_phy.c82 /* Bit position of value for lane 0 (or 2) */
84 /* Bit position of value for lane 1 (or 3) */
211 int lane; local
245 for (lane = 0; lane < 4; lane++) {
246 int count = efx_mdio_read(efx, mmd, TXC_BIST_RX0ERRCNT + lane);
249 "Lane %d had %d errs\n", lane, count);
252 count = efx_mdio_read(efx, mmd, TXC_BIST_RX0FRMCNT + lane);
255 "Lane %d got 0 frames\n", lane);
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/drivers/gpu/drm/i915/
H A Dintel_dp.c197 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
724 DRM_DEBUG_KMS("Display port link bw %02x lane "
783 * Find the lane count in the intel_encoder private
1384 int lane)
1386 int s = ((lane & 1) ?
1389 uint8_t l = adjust_request[lane>>1];
1396 int lane)
1398 int s = ((lane & 1) ?
1401 uint8_t l = adjust_request[lane>>1];
1472 int lane; local
1383 intel_get_adjust_request_voltage(uint8_t adjust_request[2], int lane) argument
1395 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2], int lane) argument
1597 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane) argument
1610 int lane; local
1630 int lane; local
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H A Dintel_display.c5679 int target_clock, pixel_multiplier, lane, link_bw, factor; local
5767 lane = 0;
5774 &lane, &link_bw);
5787 * Hence the bw of each lane in terms of the mode signal
5821 if (!lane) {
5828 lane = bps / (link_bw * 8) + 1;
5831 intel_crtc->fdi_lanes = lane;
5835 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
/drivers/gpu/drm/nouveau/
H A Dnouveau_encoder.h40 u8 lane, u8 swing, u8 preem);
H A Dnouveau_dp.c264 u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf; local
265 u8 lpre = (lane & 0x0c) >> 2;
266 u8 lvsw = (lane & 0x03) >> 0;
274 NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
314 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local
315 if (!(lane & DP_LANE_CR_DONE)) {
346 u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf; local
347 if (!(lane & DP_LANE_CR_DONE))
349 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
350 !(lane
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H A Dnv50_sor.c40 nv50_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane) argument
46 return nvaf[lane];
47 return nv50[lane];
59 u8 lane, u8 swing, u8 preem)
62 u32 shift = nv50_sor_dp_lane_map(dev, dcb, lane);
149 /* calculate packed data rate for each lane */
58 nv50_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb, u8 lane, u8 swing, u8 preem) argument
H A Dnvd0_display.c1193 nvd0_sor_dp_lane_map(struct drm_device *dev, struct dcb_entry *dcb, u8 lane) argument
1196 return nvd0[lane];
1209 u8 lane, u8 swing, u8 preem)
1213 u32 shift = nvd0_sor_dp_lane_map(dev, dcb, lane);
1208 nvd0_sor_dp_train_adj(struct drm_device *dev, struct dcb_entry *dcb, u8 lane, u8 swing, u8 preem) argument
/drivers/edac/
H A Dppc4xx_edac.h159 #define SDRAM_ECCES_BNCE_ENCODE(lane) PPC_REG_VAL(((lane) & 0xF), 1)
H A Dppc4xx_edac.c93 * nothing more than the beat/cycle and byte/lane the correction
106 * - Beat(s)/lane(s)
419 * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
421 * with the byte lane message being generated.
442 unsigned int lane, lanes; local
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
456 if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
459 (lanes++ ? ", " : ""), lane);
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/drivers/video/
H A Dsh_mipi_dsi.c239 if (!pdata->lane)
285 bitmap_fill((unsigned long *)&tmp, pdata->lane);
331 bottom = (pdata->lane * ch->lcd_modes[0].hsync_len) - 10;
352 top = ((pdata->lane * top / div) - 10) << 16;
356 bottom = (pdata->lane * bottom / div) - 12;
360 if ((pdata->lane / div) > bpp) {
363 delay = (pdata->lane * tmp);
/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c3374 u8 lane = 0; local
3405 lane = (port<<1) + path;
3420 lane = path << 1 ;
3422 return lane;
3441 * In Dual-lane mode, two lanes are joined together,
3660 u8 lane = bnx2x_get_warpcore_lane(phy, params); local
3667 lane;
3725 * i.e. reset the lane (if needed), set aer for the
3732 u16 val16 = 0, lane, bam37 = 0; local
3785 lane
3931 u16 misc1_val, tap_val, tx_driver_val, lane, val; local
4052 bnx2x_warpcore_set_20G_DXGXS(struct bnx2x *bp, struct bnx2x_phy *phy, u16 lane) argument
4212 bnx2x_warpcore_clear_regs(struct bnx2x_phy *phy, struct link_params *params, u16 lane) argument
4314 u16 gp2_status_reg0, lane; local
4332 u16 lane = bnx2x_get_warpcore_lane(phy, params); local
4398 u16 lane = bnx2x_get_warpcore_lane(phy, params); local
4569 u32 lane; local
5602 u8 lane; local
6361 u8 lane = bnx2x_get_warpcore_lane(int_phy, params); local
8390 u8 lane = bnx2x_get_warpcore_lane(phy, params); local
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