Searched refs:readl (Results 1 - 25 of 679) sorted by relevance

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/drivers/net/ethernet/stmicro/stmmac/
H A Dmmc_core.c137 u32 value = readl(ioaddr + MMC_CNTRL);
161 mmc->mmc_tx_octetcount_gb += readl(ioaddr + MMC_TX_OCTETCOUNT_GB);
162 mmc->mmc_tx_framecount_gb += readl(ioaddr + MMC_TX_FRAMECOUNT_GB);
163 mmc->mmc_tx_broadcastframe_g += readl(ioaddr + MMC_TX_BROADCASTFRAME_G);
164 mmc->mmc_tx_multicastframe_g += readl(ioaddr + MMC_TX_MULTICASTFRAME_G);
165 mmc->mmc_tx_64_octets_gb += readl(ioaddr + MMC_TX_64_OCTETS_GB);
167 readl(ioaddr + MMC_TX_65_TO_127_OCTETS_GB);
169 readl(ioaddr + MMC_TX_128_TO_255_OCTETS_GB);
171 readl(ioaddr + MMC_TX_256_TO_511_OCTETS_GB);
173 readl(ioadd
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H A Ddwmac100_core.c37 u32 value = readl(ioaddr + MAC_CONTROL);
58 readl(ioaddr + MAC_CONTROL));
60 readl(ioaddr + MAC_ADDR_HIGH));
62 readl(ioaddr + MAC_ADDR_LOW));
64 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
66 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
68 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
70 readl(ioaddr + MAC_VLAN1));
72 readl(ioaddr + MAC_VLAN2));
95 u32 value = readl(ioadd
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H A Ddwmac100_dma.c38 u32 value = readl(ioaddr + DMA_BUS_MODE);
46 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
74 u32 csr6 = readl(ioaddr + DMA_CONTROL);
94 readl(ioaddr + DMA_BUS_MODE + i * 4));
96 DMA_CUR_TX_BUF_ADDR, readl(ioaddr + DMA_CUR_TX_BUF_ADDR));
98 DMA_CUR_RX_BUF_ADDR, readl(ioaddr + DMA_CUR_RX_BUF_ADDR));
107 u32 csr8 = readl(ioaddr + DMA_MISSED_FRAME_CTR);
H A Ddwmac1000_core.c36 u32 value = readl(ioaddr + GMAC_CONTROL);
51 u32 value = readl(ioaddr + GMAC_CONTROL);
56 value = readl(ioaddr + GMAC_CONTROL);
69 offset, readl(ioaddr + offset));
146 "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
147 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
192 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
197 readl(ioaddr + GMAC_MMC_TX_INTR));
200 readl(ioadd
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H A Ddwmac1000_dma.c36 u32 value = readl(ioaddr + DMA_BUS_MODE);
44 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
74 u32 csr6 = readl(ioaddr + DMA_CONTROL);
131 readl(ioaddr + DMA_BUS_MODE + offset));
138 return readl(ioaddr + DMA_HW_FEATURE);
/drivers/video/mbx/
H A Dmbxdebugfs.c35 s += sprintf(s, "SYSCFG = %08x\n", readl(SYSCFG));
36 s += sprintf(s, "PFBASE = %08x\n", readl(PFBASE));
37 s += sprintf(s, "PFCEIL = %08x\n", readl(PFCEIL));
38 s += sprintf(s, "POLLFLAG = %08x\n", readl(POLLFLAG));
39 s += sprintf(s, "SYSRST = %08x\n", readl(SYSRST));
51 s += sprintf(s, "GSCTRL = %08x\n", readl(GSCTRL));
52 s += sprintf(s, "VSCTRL = %08x\n", readl(VSCTRL));
53 s += sprintf(s, "GBBASE = %08x\n", readl(GBBASE));
54 s += sprintf(s, "VBBASE = %08x\n", readl(VBBASE));
55 s += sprintf(s, "GDRCTRL = %08x\n", readl(GDRCTR
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/drivers/media/video/s5p-mfc/
H A Ds5p_mfc_opr.h56 #define s5p_mfc_get_dspl_y_adr() (readl(dev->regs_base + \
59 #define s5p_mfc_get_dec_y_adr() (readl(dev->regs_base + \
62 #define s5p_mfc_get_dspl_status() readl(dev->regs_base + \
64 #define s5p_mfc_get_frame_type() (readl(dev->regs_base + \
67 #define s5p_mfc_get_consumed_stream() readl(dev->regs_base + \
69 #define s5p_mfc_get_int_reason() (readl(dev->regs_base + \
72 #define s5p_mfc_get_int_err() readl(dev->regs_base + \
78 #define s5p_mfc_get_img_width() readl(dev->regs_base + \
80 #define s5p_mfc_get_img_height() readl(dev->regs_base + \
82 #define s5p_mfc_get_dpb_count() readl(de
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/drivers/media/video/s5p-jpeg/
H A Djpeg-hw.h37 reg = readl(regs + S5P_JPG_SW_RESET);
41 reg = readl(regs + S5P_JPG_SW_RESET);
60 reg = readl(regs + S5P_JPGCMOD);
70 reg = readl(regs + S5P_JPGCMOD);
87 reg = readl(regs + S5P_JPGMOD);
102 reg = readl(regs + S5P_JPGMOD);
110 return readl(regs + S5P_JPGMOD) & S5P_SUBSAMPLING_MODE_MASK;
117 reg = readl(regs + S5P_JPGDRI_U);
122 reg = readl(regs + S5P_JPGDRI_L);
132 reg = readl(reg
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/drivers/misc/ibmasm/
H A Dlowlevel.h57 return SP_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
62 return UART_INTR_MASK & readl(base_address + INTR_STATUS_REGISTER);
68 writel( readl(ctrl_reg) & ~mask, ctrl_reg);
74 writel( readl(ctrl_reg) | mask, ctrl_reg);
105 mfa = readl(base_address + OUTBOUND_QUEUE_PORT);
119 u32 mfa = readl(base_address + INBOUND_QUEUE_PORT);
/drivers/video/exynos/
H A Dexynos_mipi_dsi_lowlevel.c36 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
47 reg = readl(dsim->reg_base + EXYNOS_DSIM_SWRST);
58 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTSRC);
67 return (readl(dsim->reg_base + EXYNOS_DSIM_INTSRC)) &
75 reg = readl(dsim->reg_base + EXYNOS_DSIM_INTMSK);
98 reg = readl(dsim->reg_base + EXYNOS_DSIM_FIFOCTRL);
121 reg = readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL);
137 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MDRESOL)) &
153 reg = (readl(dsim->reg_base + EXYNOS_DSIM_MVPORCH)) &
169 reg = (readl(dsi
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H A Dexynos_dp_reg.c35 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
39 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
49 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
162 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
174 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
178 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
193 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
197 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
204 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
208 reg = readl(d
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/drivers/scsi/qla4xxx/
H A Dql4_inline.h44 readl(&ha->reg->u1.isp4022.intr_mask);
47 readl(&ha->reg->ctrl_status);
58 readl(&ha->reg->u1.isp4022.intr_mask);
61 readl(&ha->reg->ctrl_status);
/drivers/usb/dwc3/
H A Dio.h46 return readl(base + offset);
/drivers/block/
H A Dcciss.h227 readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
244 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
250 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
264 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
270 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
280 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
285 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
308 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
334 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
341 register_value = readl(
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/drivers/scsi/bfa/
H A Dbfa_ioc_ct.c68 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
75 readl(ioc->ioc_regs.ioc_usage_sem_reg);
82 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
95 readl(ioc->ioc_regs.ioc_usage_sem_reg);
106 readl(ioc->ioc_regs.ioc_usage_sem_reg);
128 usecnt = readl(ioc->ioc_regs.ioc_usage_reg);
135 readl(ioc->ioc_regs.ioc_usage_sem_reg);
149 readl(ioc->ioc_regs.ll_halt);
150 readl(ioc->ioc_regs.alt_ll_halt);
153 readl(io
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/drivers/net/ethernet/intel/ixgb/
H A Dixgb_osdep.h52 readl((a)->hw_addr + IXGB_##reg))
58 readl((a)->hw_addr + IXGB_##reg + ((offset) << 2)))
/drivers/scsi/lpfc/
H A Dlpfc_compat.h31 using writel() and readl().
51 readl(dest32); /* flush */
72 *dest32 = readl( src32);
/drivers/scsi/pm8001/
H A Dpm8001_chips.h57 return readl(pm8001_ha->io_mem[bar].memvirtaddr + offset);
67 return readl(addr + offset);
/drivers/clocksource/
H A Dcyclone.c24 return (cycle_t)readl(cyclone_ptr);
57 base = readl(reg);
94 u32 old = readl(cyclone_timer);
100 if (readl(cyclone_timer) == old) {
H A Dclksrc-dbx500-prcmu.c41 count = readl(clksrc_dbx500_timer_base +
43 count2 = readl(clksrc_dbx500_timer_base +
81 if (readl(clksrc_dbx500_timer_base + PRCMU_TIMER_MODE) !=
/drivers/gpu/drm/gma500/
H A Dpsb_lid.c35 if (readl(lid_state) == dev_priv->lid_last_state)
38 if ((readl(lid_state)) & 0x01) {
55 dev_priv->lid_last_state = readl(lid_state);
/drivers/rtc/
H A Drtc-puv3.c41 writel(readl(RTC_RTSR) | RTC_RTSR_AL, RTC_RTSR);
50 writel(readl(RTC_RTSR) | RTC_RTSR_HZ, RTC_RTSR);
62 tmp = readl(RTC_RTSR) & ~RTC_RTSR_ALE;
77 tmp = readl(RTC_RTSR) & ~RTC_RTSR_HZE;
91 rtc_time_to_tm(readl(RTC_RCNR), rtc_tm);
118 rtc_time_to_tm(readl(RTC_RTAR), alm_tm);
120 alrm->enabled = readl(RTC_RTSR) & RTC_RTSR_ALE;
156 (readl(RTC_RTSR) & RTC_RTSR_HZE) ? "yes" : "no");
213 writel(readl(RTC_RTSR) & ~RTC_RTSR_HZE, RTC_RTSR);
216 if ((readl(RTC_RTS
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/drivers/i2c/busses/
H A Di2c-pxa.c250 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
262 readl(_ICR(i2c)), readl(_ISR(i2c)));
285 return !(readl(_ICR(i2c)) & ICR_SCLE);
297 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
298 unsigned long icr = readl(_ICR(i2c));
311 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
319 while (timeout-- && readl(_IS
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/drivers/scsi/
H A Dhpsa.h218 (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
234 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
239 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
248 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
253 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
264 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
271 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
309 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
330 readl(h->vaddr + SA5_INTR_STATUS);
337 unsigned long register_value = readl(
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/drivers/tty/serial/
H A Dnetx-serial.c121 val = readl(port->membase + UART_CR);
128 val = readl(port->membase + UART_CR);
135 val = readl(port->membase + UART_CR);
164 } while (!(readl(port->membase + UART_FR) & FR_TXFF));
173 readl(port->membase + UART_CR) | CR_TIE, port->membase + UART_CR);
175 if (!(readl(port->membase + UART_FR) & FR_TXFF))
181 return readl(port->membase + UART_FR) & FR_BUSY ? 0 : TIOCSER_TEMT;
204 while (!(readl(port->membase + UART_FR) & FR_RXFE)) {
205 rx = readl(port->membase + UART_DR);
208 status = readl(por
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