| 1c3781496081b47412fc70393bcdc5b67b440b02 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Support fpv4 for ARM Cortex-M4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161163 91177308-0d34-0410-b5e6-96231b3b80d8
fp4.s
|
| fd652df8b36a9d3e6b09ae2b9f7bcb07e88fdfaa |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| c1b7ca5ba28ded2d83ae534c8e072c2538d43295 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb2-instructions.s
|
| 1fb27eccf5b7eabde9678d84411eb1df8a693683 |
02-Aug-2012 |
Jiangning Liu <jiangning.liu@arm.com> |
Fix #13241, a bug around shift immediate operand for ARM instruction ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161159 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb2-instructions.s
|
| fae96f17b4b022fccd94a143698112a17d8ddf05 |
10-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters) (and do it properly this time!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159989 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 270e3625b23174688aa5b6f1e1d0cd42086541de |
09-Jul-2012 |
Chad Rosier <mcrosier@apple.com> |
Revert r159938 (and r159945) to appease the buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 2e7e34ba5485320a84ca69c83d242e24433f7acd |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 8ed97ef5f6980c689a5770ec30488601201e17c3 |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Prevent ARM assembler from losing a right shift by #32 applied to a register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 2b6652fb10d7005e41010b0e0800afe16ae18a34 |
09-Jul-2012 |
Richard Barton <richard.barton@arm.com> |
Teach the assembler to use the narrow thumb encodings of various three-register dp instructions where permissable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935 91177308-0d34-0410-b5e6-96231b3b80d8
humb2-narrow-dp.ll
|
| 4acefe192f02849bcb2fd620a9f507c00d39a686 |
27-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Teach assembler to handle capitalised operation values for DSB instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159259 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 70c9bf3c1a77b5707c92a7cfe74104c320480391 |
23-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add a better diagnostic for some out of range immediates.
As an example of how the custom DiagnosticType can be used to provide
better operand-mismatch diagnostics, add a custom diagnostic for
the imm0_15 operand class used for several system instructions.
Update the tests to expect the improved diagnostic.
rdar://8987109
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159051 91177308-0d34-0410-b5e6-96231b3b80d8
iagnostics.s
humb2-diagnostics.s
|
| c9a4e269d00dc9e2ba0c7b77721fa54cfb5a59fa |
19-Jun-2012 |
Jan Wen Voung <jvoung@google.com> |
Have ARM ELF use correct reloc for "b" instr.
The condition code didn't actually matter for arm "b" instructions,
unlike "bl". It should just use the R_ARM_JUMP24 reloc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158722 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-condcall.s
|
| 7e99a60857532ca2973cf9dabc790d84a2e15a8a |
18-Jun-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Define generic HINT instruction.
The NOP, WFE, WFI, SEV and YIELD instructions are all hints w/
a different immediate value in bits [7,0]. Define a generic HINT
instruction and refactor NOP, WFI, WFI, SEV and YIELD to be
assembly aliases of that.
rdar://11600518
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158674 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb2-instructions.s
|
| f49a4092bcf679d1634a8023efc593e98a3e5663 |
16-Jun-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
humb2-mclass.s
|
| a1c7367a5bed459acc88e3ea2a482b4b5dac942a |
14-Jun-2012 |
Richard Barton <richard.barton@arm.com> |
Replace assertion failure for badly formatted CPS instrution with error message.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158445 91177308-0d34-0410-b5e6-96231b3b80d8
iagnostics.s
|
| 3e96531186ba574b0c25a4be62d24b8b7d752c9f |
18-May-2012 |
Jim Grosbach <grosbach@apple.com> |
Refactor data-in-code annotations.
Use a dedicated MachO load command to annotate data-in-code regions.
This is the same format the linker produces for final executable images,
allowing consistency of representation and use of introspection tools
for both object and executable files.
Data-in-code regions are annotated via ".data_region"/".end_data_region"
directive pairs, with an optional region type.
data_region_directive := ".data_region" { region_type }
region_type := "jt8" | "jt16" | "jt32" | "jta32"
end_data_region_directive := ".end_data_region"
The previous handling of ARM-style "$d.*" labels was broken and has
been removed. Specifically, it didn't handle ARM vs. Thumb mode when
marking the end of the section.
rdar://11459456
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157062 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-01.ll
|
| 0fd4f3c8de07e9cfe2a86093ccada82d64f38bfe |
18-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
humb2-mclass.s
|
| ca3cd419a52c1dedee133d79772ef97f30e5d20b |
11-May-2012 |
Silviu Baranga <silviu.baranga@arm.com> |
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156608 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 2d524b0765145f1c7888166c985a25452f16b2bc |
04-May-2012 |
Kevin Enderby <enderby@apple.com> |
Fix issues with the ARM bl and blx thumb instructions and the J1 and J2 bits
for the assembler and disassembler. Which were not being set/read correctly
for offsets greater than 22 bits in some cases.
Changes to lib/Target/ARM/ARMAsmBackend.cpp from Gideon Myles!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156118 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 2727930ab4ce260fef0487bc878c1cd4c3769cef |
02-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add missing two-operand VBIC aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156019 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| 0a552d611efe9d1070aff1d35c7f169dd1ab0be7 |
02-May-2012 |
Richard Barton <richard.barton@arm.com> |
Disallow YIELD and other allocated nop hints in pre-ARMv6 architectures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155983 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
humb.s
|
| 54319e2a8c22e7ee7044e398fbd8d4287e2b7c4f |
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add a few missing add->sub aliases w/ 'w' suffix.
Aliases for adding a negative immediate when using an explicit 'w'
suffix. E.g.,
adds.w r2, #-16
adds.w r2, r2, #-16
addw r2, #-16
addw r2, #-16
addw r2, r2, #-16
rdar://11330769
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155946 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 94b590f8faf4dbba406f263e6a839882b0c68a94 |
01-May-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: allow vanilla expressions for movw/movt.
Expressions for movw/movt don't always have an :upper16: or :lower16:
on them and that's ok. When they don't, it's just a plain [0-65536]
immediate result, effectively the same as a :lower16: variant kind.
rdar://10550147
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155941 91177308-0d34-0410-b5e6-96231b3b80d8
rm_fixups.s
|
| a9cc08f24f61e2663a131d7ac16c329b75162e7b |
28-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Thumb add(sp plus register) asm constraints.
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.
rdar://11219154
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155748 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
humb-diagnostics.s
|
| 04a09a461beb4ec629fe53e601b7665547ac35c3 |
27-Apr-2012 |
Richard Barton <richard.barton@arm.com> |
Fix ARM assembly parsing for upper case condition codes on IT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155720 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| cac31de146e7131f411715dc6cb1958ea59bd754 |
26-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Specify cpu to unbreak tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155604 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb2-instructions.s
eont2-absdiff-encoding.s
eont2-dup-encoding.s
push-vpop.s
|
| 14ce6fac242228dacc5c08040e544141a96880e5 |
25-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: improved assembler diagnostics for missing CPU features.
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.
rdar://11257547
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155499 91177308-0d34-0410-b5e6-96231b3b80d8
humb-diagnostics.s
|
| c34954d432cce4bf09d30b3ec13e46d577909fa7 |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Add testcases for two-operand variants of VSRA/VRSRA/VSRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155391 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shiftaccum-encoding.s
eont2-shiftaccum-encoding.s
|
| 10a3933c5f03e331b1d3912c0f0eb37bacb152ca |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode tests for the NEON vector shift-accumulate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155390 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shiftaccum-encoding.s
|
| 2b8525068a9b90760d9286a2f4802470b844303d |
23-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Reformat for ease of reading.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155389 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-shiftaccum-encoding.s
|
| d8b3ed8f25c1ba76a6db875cd2d6eaa016bd4646 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM: Update NEON assembly two-operand aliases.
Use the new TwoOperandAliasConstraint to handle lots of the two-operand aliases
for NEON instructions. There's still more to go, but this is a good chunk of
them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155210 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
eon-sub-encoding.s
|
| 181b14797518e714e1b6112db849ca53192b8f23 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM some VFP tblgen'erated two-operand aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155178 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| bfb3c5a50c0c01073658ec9d3504532c6eeb2115 |
20-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155177 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| bf42f24e6e2347fbd28abb9d442a6cd9d95fcc3b |
17-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand forms for vhadd and vhsub instructions.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
eon-add-encoding.s
eon-sub-encoding.s
|
| 199366a6a6b59717cd1b98d8d5df521e3981de19 |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly two-operand forms for VRSHL.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154840 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 695eca66b1b7b429f2b3d2ae1d583a426cb9c227 |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Test formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154839 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 705e2572b442c34d65a3b667e008327b50bac06b |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VRHADD instructions.
rdar://11252521
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8
eon-add-encoding.s
|
| dbd6ba36e44d822054574f2013809e0f027853dd |
16-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Testcase formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154831 91177308-0d34-0410-b5e6-96231b3b80d8
eon-add-encoding.s
|
| 1835547ec195c35b3a59bf834f4df942c61a5c53 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM 'vuzp.32 Dd, Dm' is a pseudo-instruction.
While there is an encoding for it in VUZP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.
rdar://11222366
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154511 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.s
|
| 6073b30b053da2c2ac6150dd67cecb304bc614f1 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM 'vzip.32 Dd, Dm' is a pseudo-instruction.
While there is an encoding for it in VZIP, the result of that is undefined,
so we should avoid it. Define the instruction as a pseudo for VTRN.32
instead, as the ARM ARM indicates.
rdar://11221911
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154505 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.s
|
| bee78fe5fcd8464f58bc729dede1a87d763ac3ae |
11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Clean up ARM fused multiply + add/sub support some more: rename some isel
predicates.
Also remove NEON2 since it's not really useful and it is confusing. If
NEON + VFP4 implies NEON2 but NEON2 doesn't imply NEON + VFP4, what does it
really mean?
rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154480 91177308-0d34-0410-b5e6-96231b3b80d8
fp4.s
|
| a5378ebe7890aa9a4974f2872aa6632f1b7f2400 |
11-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM add missing Thumb1 two-operand aliases for shift-by-immediate.
rdar://11222742
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154457 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 82509e5c62a99912c636b22e227b810eaf6eda78 |
11-Apr-2012 |
Evan Cheng <evan.cheng@apple.com> |
Fix a number of problems with ARM fused multiply add/subtract instructions.
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154456 91177308-0d34-0410-b5e6-96231b3b80d8
fp4.s
|
| a23ecc2ba945c9685a76552276e5f6f41859b4ab |
10-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM fix cc_out operand handling for t2SUBrr instructions.
We were incorrectly conflating some add variants which don't have a
cc_out operand with the mirroring sub encodings, which do. Part of the
awesome non-orthogonality legacy of thumb1. Similarly, handling of
add/sub of an immediate was sometimes incorrectly removing the cc_out
operand for add/sub register variants.
rdar://11216577
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154411 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 4e53fe8dc61ad48650ac6fe30d7268ec92b7fc1a |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for add negative immediates using sub.
'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out.
Thumb1 aliases for adding a negative immediate to the stack pointer,
also.
rdar://11192734
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154123 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 22378fd664fed97c296878d8d188ab06e2c89395 |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for two-operand V[R]SHR instructions.
rdar://11189467
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154087 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| b657a90929867716ca1c7c12d442bb5d32281bd4 |
05-Apr-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for 'msr' plain 'cpsr' operand.
Plain 'cpsr' is an alias for 'cpsr_fc'.
rdar://11153753
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154080 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ad353c630359d285018a250d72c80b7022d8e67e |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler should prefer non-aliases encoding of cmp.
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153770 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| a45e3747e612c00ca4933087d883db77f4547571 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding for VSWP got the second operand incorrect.
Make the non-tied register operand names line up with what the base
class encoding handler expects.
rdar://11157236
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vswp.s
|
| 2d30d947ec2626e8b1a9b577cdfa4121f476c3f5 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM integrated assembler should encoding choice for add/sub imm.
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.
rdar://11156277
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153759 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| c0164f86080bc9d7a41fd5eabd0d6556396f5b38 |
30-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing needs to be paranoid about negative immediates.
Make sure to treat immediates as unsigned when doing relative comparisons.
rdar://11153621
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153753 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| cb0809b82b126e79b99755ae4fc3d9733faea038 |
30-Mar-2012 |
James Molloy <james.molloy@arm.com> |
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.
Patch by Tim Northover!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
rm_fixups.s
asic-arm-instructions.s
lf-reloc-condcall.s
|
| b22e70d835a88753d3ec6d5ee5e85b23fa6834b1 |
29-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.
rdar://11129224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 6e9d66c756a3d3f0d1636a9f1143dedd2f58138b |
28-Mar-2012 |
Richard Barton <richard.barton@arm.com> |
Fixup VST1.32 with writeback instruction. Also re-factor non-writeback version.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153573 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| cc85160672e3b2d5ec363cc4e151e5b944a60454 |
25-Mar-2012 |
Eli Bendersky <eli.bendersky@intel.com> |
Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu
* Removed test/lib/llvm.exp - it is no longer needed
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
left in the test suite so this code is no longer required. test/lit.cfg is
now much shorter and clearer
* Removed a lot of duplicate code in lit.local.cfg files that need access to
the root configuration, by adding a "root" attribute to the TestingConfig
object. This attribute is dynamically computed to provide the same
information as was previously provided by the custom getRoot functions.
* Documented the config.root attribute in docs/CommandGuide/lit.pod
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153408 91177308-0d34-0410-b5e6-96231b3b80d8
it.local.cfg
|
| 9f2e160f7ae90a7a80b17e38ad06f2c706515115 |
20-Mar-2012 |
Kevin Enderby <enderby@apple.com> |
Fix assembling ARM vst2 instructions with double-spaced registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
eont2-vst-encoding.s
|
| be7cf2b377d987f46d10f54f89ae4e1a71c37f55 |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM ldm/stm register lists can be out of order.
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152943 91177308-0d34-0410-b5e6-96231b3b80d8
iagnostics.s
|
| 213d2e7dc31bef3ceeef0cefa703cb4ce52de51a |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM optional operand on MRC/MCR assembly instructions.
rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152883 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 9426ac7b575de9e1297a01f27307d858343ac4ed |
16-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM vmrs system registers mvfr0 and mvfr1 handling.
rdar://11058464
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152881 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| b84ad4aa7dacfba5337520740d47770f2200201c |
15-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM case-insensitive checking for APSR_nzcv.
rdar://11056591
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152846 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 8a6bcc3722729803a16b5885de1ff85a3752e6a0 |
15-Mar-2012 |
Kristof Beyls <kristof.beyls@arm.com> |
Fix VCVT decoding (between floating-point and fixed-point, Floating-point). Patch by Richard Barton.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152814 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| bc978a60d90a06b2d879b6f4db22b3760168df7f |
06-Mar-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM vpush/vpop assembler mnemonics accept an optional size suffix.
rdar://10988114
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152068 91177308-0d34-0410-b5e6-96231b3b80d8
push-vpop.s
|
| 7b25ecf6adbf3c4709c48033acfeb6ebbb4452ab |
27-Feb-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM BL/BLX instruction fixups should use relocations.
We on the linker to resolve calls to the appropriate BL/BLX instruction
to make interworking function correctly. It uses the symbol in the
relocation to do that, so we need to be careful about being too clever.
To enable this for ARM mode, split the BL/BLX fixup kind off from the
unconditional-branch fixups.
rdar://10927209
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151571 91177308-0d34-0410-b5e6-96231b3b80d8
rm_fixups.s
asic-arm-instructions.s
|
| 0f0c411079cd21bb3a81a1b70bf8c67539a16c22 |
16-Feb-2012 |
Eli Bendersky <eli.bendersky@intel.com> |
Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed.
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150664 91177308-0d34-0410-b5e6-96231b3b80d8
g.exp
it.local.cfg
|
| 2d8955a77c6920d1a50de5ec9094faaa1b2f4e88 |
28-Jan-2012 |
James Molloy <james.molloy@arm.com> |
Ensure .AliasedSymbol() is called on all uses of getSymbol(). Affects ARM and MIPS ELF backends.
Fixes PR11877
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149180 91177308-0d34-0410-b5e6-96231b3b80d8
r11877.s
|
| 34982576a43887e7f062ed0a3571af2cbab003f3 |
26-Jan-2012 |
James Molloy <james.molloy@arm.com> |
Add support for the R_ARM_TARGET1 relocation, which should be given to relocations applied to all C++ constructors and destructors.
This enables the linker to match concrete relocation types (absolute or relative) with whatever library or C++ support code is being linked against.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149057 91177308-0d34-0410-b5e6-96231b3b80d8
xx-global-constructor.ll
|
| 74423e32ce7f426b624bfb0c31481bcf6a36394d |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
ARM assemly parsing and validation of IT instruction.
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148969 91177308-0d34-0410-b5e6-96231b3b80d8
rm-it-block.s
|
| a57a36abe7d0b769a495ed886246db157aff4add |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 5e59f7e15ed3770b32481cd72d2c15b159e991e6 |
25-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148882 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 88a54de799240d5de2e79dfff4671ad5653e7ceb |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST4(one lane) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148836 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| e983a134e7e40e214f590c3d8ba565bb85f39628 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(one lane) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148832 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 1ac2060678edd88726e06ff19c9468211b41fc37 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSRA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148821 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 5d9bad40980c0b605f9d69bfa1374292f874a3d7 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148820 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shiftaccum-encoding.s
|
| 5e497d39927d2ddf6bf6adbfac39fe9102a1a305 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148819 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| d8ee0cc4e8b67f9d85d08bd55e53ac14c5ca533d |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON Two-operand assembly aliases for VSRI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148818 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 28f1f9100f33388f9f439c16051185a2cd0e9388 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148817 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 539aab771fea06bd230789e19c9672ef80ad1c7e |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| 8abe7e33641fccfa70a7e335939e83dfbf654fe8 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD4(multiple 4 element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148762 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 4adb18234278d6d40e5791e0dd6970be9a4b0b57 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST3(single element from one lane) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| d7433e2873706265d545edc5cdd0a728dd71ef66 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VST3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| c387fc66bd52e4276fdc2704a3aaed57cc1f9a11 |
24-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3(multiple 3-element structures) assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148745 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
eon-vst-encoding.s
|
| 3a678af71dec76a7e1474ad85a99b3588516906d |
23-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON VLD3 lane-indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148734 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| 8b31f95bdde1e3809a1c9fdb6926b1840effcf9c |
23-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Simplify some NEON assembly pseudo definitions.
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| 51222d1551383dd7b95ba356b1a5ed89df69e789 |
20-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
NEON use vmov.i32 to splat some f32 values into vectors.
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 0b4c6738868e11ba06047a406f79489cb1db8c5a |
18-Jan-2012 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alternate syntax for LDR(literal) and friends.
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148432 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 4050bc4cab61f8d3c7583a9b60f17c7da47bbf69 |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
rdar://10558523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| b975c27adc2371a9666fa9b8cecd9487966ec5b1 |
22-Dec-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Fix incorrect relocation generation. Patch by Kristof Beyls.
Fixes PR11214.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147180 91177308-0d34-0410-b5e6-96231b3b80d8
lf-thumbfunc-reloc.s
|
| 8d9550bde95c8d128e7bf62e9e65dec1854e2d1d |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147153 91177308-0d34-0410-b5e6-96231b3b80d8
rm-aliases.s
|
| af33a0cfe092afd327e1b8b05c655d9eab689eed |
22-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VFP optional data type on VMOV GPR<-->SPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 520dc78d92a47af5e644b09f401d278cb1d5d196 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147096 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 2cc5cda464e7c936215281934193658cb799c603 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147094 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| e6949b13997e6d31aa4719a0e80c4b6b405e42a9 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147069 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 3471d4fbbd50eabb12511b711cbd2afd7bb9d962 |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147025 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 06d738c76a1ce4fe17fa8fc4a62288a09d1ae5ec |
21-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable and fix a test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147011 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-encoding.s
|
| 5b484312c66f8d125c072517947538f301c5a805 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VST2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| 514806b52e88aca0c30f55763a997d1befa7c2ba |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM enable a few more tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| 95fad1c6034cdf8010428e61b71cd196ee1698ad |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146983 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 04b5d93250bef585631a583a85f6733b1bdc8c52 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly shifts by zero should be plain 'mov' instructions.
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146937 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 2f196747f15240691bd4e622f7995edfedf90f61 |
20-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for LDRD(label).
rdar://9932658
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146921 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| d22170e16a42aed0212e1e52f189bfb8b7c7105d |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VPADD.
rdar://10602276
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146895 91177308-0d34-0410-b5e6-96231b3b80d8
eon-pairwise-encoding.s
|
| 61b74b42478474534827070cdd703811ddc9ce19 |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON implied destination aliases for VMAX/VMIN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146885 91177308-0d34-0410-b5e6-96231b3b80d8
eon-minmax-encoding.s
eont2-minmax-encoding.s
|
| eeaf1c1636c664c707fd9ecc96916fd20ddf137a |
19-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON relax parse time diagnostics for alignment specifiers.
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146884 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| a738da7bd30819f1bc710d313c9ecb06c56f1a4f |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.s
|
| 60d99a5278e4a0e7116a05c01cececb07ca1362a |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VTBL/VTBX assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146691 91177308-0d34-0410-b5e6-96231b3b80d8
eon-table-encoding.s
eont2-table-encoding.s
|
| 9b1b3902882675e5ce35eacd639456bd648324b7 |
15-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
eon-vst-encoding.s
|
| ec04a3f8db9ab9db3bbec3ce32baaa2ea2cb853f |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON fix alignment encoding for VST2 w/ writeback.
Add tests for w/ writeback instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| e90ac9bce9aa6de288568df9bf6133c08534ae2f |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VST2 assembly parsing and encoding.
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| 8d11c6349f9bf276534907245946518042c1bb60 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146567 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb2-instructions.s
|
| a39cda7aff2d379ad9c15500319ab037baa48747 |
14-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for the target-specific .req directive.
rdar://10549683
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146543 91177308-0d34-0410-b5e6-96231b3b80d8
ot-req.s
|
| 863d2af9477e331955a9bee8be1969ce658b59b5 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembler aliases for "mov(shifted register)"
rdar://10549767
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146520 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 27debd60a152d39e421c57bce511f16d8439a670 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDM/STM system instruction variants.
rdar://10550269
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146519 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 0da6e867cf10a0bcca56df8d854355025e1d6f91 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Test for 146516
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146517 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 55b02f28c1a2960ebb88cf5019cc5b36bb2eabf4 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM thumb2 parsing of "rsb rd, rn, #0".
rdar://10549741
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146515 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 0f293de207fa0e9461a9dbee95bed9a6a2c52f76 |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VQDMULH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146514 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.s
|
| e91e7bcadc445381adef5c5154e8e2cba074505f |
13-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pre-UAL NEG mnemonic for convenience when porting old code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146511 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb2-instructions.s
|
| 840bf7eda7c81059a0aae9abd51262147c60d814 |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly aliases for BIC<-->AND (immediate).
When the immediate operand of an AND or BIC instruction isn't representable
in the immediate field of the instruction, but the bitwise negation of the
immediate is, assemble the instruction as the inverse operation instead
with the inverted immediate as the operand.
rdar://10550057
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146283 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| a4e3c7fc4ba2d55695b0484480685698132eba20 |
09-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD2 with writeback.
Refactor the instructions into fixed writeback and register-stride
writeback variants to simplify the offset operand (no more optional
register operand using reg0). This is a simpler representation and allows
the assembly parser to more easily handle these instructions.
Add tests for the instruction variants now supported.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146278 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 8759c3f548e03f7caff45f35fde49ed3e8c1cf71 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM 64-bit VEXT assembly uses a .64 suffix, not .32, amazingly enough.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146194 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.s
|
| 6b044c26094a9f86da7d12945b00a47a5f07cf6d |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VSHR implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146192 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 318df74104459156222968792018f29a0a530ae3 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146190 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 120313435d217d869bd2141b0cd8f4d99ae4b9a4 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VSUB implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146182 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.s
|
| beef39ab6326ed162aceb9d2e4ceef98d51d40b2 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146181 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.s
|
| 9e7b42a40eb8fbeac92ad2272d983d559a554c37 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VQADD implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146179 91177308-0d34-0410-b5e6-96231b3b80d8
eon-add-encoding.s
|
| 1c2c8a9389526518164ab6386ffcd6a1fa01124d |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM a few more VMUL implied destination operand form aliases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146177 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.s
|
| 730fe6c1b686fe71c8e549b0f955e65a6a49d3ff |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VSHL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146125 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| ff4cbb4c9a66d313a9f52830620f06c88b43397c |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON two-operand aliases for VSHL(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146123 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| a44f2c4a28cd9c43a3d34cbad4f47df77ec686cf |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM optional destination operand variants for VEXT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146114 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.s
|
| 71a0a2ec0b367ecbbe1b6e8b528d65c738d7c2d6 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146113 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.s
|
| 3bc8a3d3afe3ddda884a681002e24850099b719e |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler aliases for "add Rd, #-imm" to "sub Rd, #imm".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146111 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| af4edea67b007592f9474e07d27182956e37f7f5 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly, allow 'asl' as a synonym for 'lsl' in shifted-register operands.
For 'gas' compatibility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146106 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 9fa0a743e6afef4ea5fe7b5115607947696774a8 |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VAND/VEOR/VORR instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146095 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| 30a264eb7fa6c961e94a7eb3d3eaf72d9bc8a44c |
08-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VADDW instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146093 91177308-0d34-0410-b5e6-96231b3b80d8
eon-add-encoding.s
|
| d900441e134564aa396522ab6e4617a98db91e34 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM two-operand aliases for VADD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146091 91177308-0d34-0410-b5e6-96231b3b80d8
eon-add-encoding.s
|
| 8524bca75076a5e94ba3263968fa4b9e4fc6234f |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 alias for long-form pop and friends.
rdar://10542474
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146046 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 9a70df99ca674b288d50dbf454779ed75d6e48dd |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM support the .arm and .thumb directives for assembly mode switching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146042 91177308-0d34-0410-b5e6-96231b3b80d8
ode-switch.s
|
| 470855b24ff4e82360ce1f84a1088332f3b4c8ea |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON VCLT(register) is a pseudo aliasing VCGT(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146039 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.s
|
| d552a644bec41fe137712c9185d4ca4b0bb54489 |
07-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Move MachO tests to MachO directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146038 91177308-0d34-0410-b5e6-96231b3b80d8
arwin-ARM-reloc.s
arwin-Thumb-reloc.s
op-armv4-padding.s
op-armv6t2-padding.s
op-thumb-padding.s
op-thumb2-padding.s
humb2-movt-fixup.s
|
| 18851edbc4666a8c8695b294e8bdfabbe157c086 |
06-Dec-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
test/MC: Introduce MC/MachO/ARM, and relocate relax-thumb2-branches.s into it.
FIXME: Restore more other arch-dependent MachO tests. (eg. r126401 and r133856)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145925 91177308-0d34-0410-b5e6-96231b3b80d8
elax-thumb2-branches.s
|
| 23261af193e462b73257445053f9f6515e60e8c9 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM mode 'mul' operand ordering tweak.
Same as r145922, just for ARM mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145923 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| cf9814ddd277dfcbb4ec5727e2cb510b8a451e04 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2: MUL two-operand form encoding operand order fix.
Fix the alias to encode 'mul r5, r6' as if it were 'mul r5, r6, r5' so we
match gas.
rdar://10532439
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145922 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| df33e0d05e6b7dc3d65cdb96e52fb6fb6b07f876 |
06-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 encoding choice correction for PLD.
Using encoding T1 for offset of #0 and encoding T2 for #-0.
rdar://10532413
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145919 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 286ea03382a5daa1b20f780f40807f1a0257a62e |
06-Dec-2011 |
NAKAMURA Takumi <geek4civic@gmail.com> |
test/MC: Move relax-thumb2-branches.s from MC/MachO/ to MC/ARM.
MC/MachO assumes x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145916 91177308-0d34-0410-b5e6-96231b3b80d8
elax-thumb2-branches.s
|
| 713c70238c6d150d2cd458b07ab35932fafe508e |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ADDrr fix. Bad check for explicit .w
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145863 91177308-0d34-0410-b5e6-96231b3b80d8
ode-switch.s
|
| 6e507c645d469f525a46c4280cc29bd3078bb9d0 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Update tests for r145860. Add a few new ones.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145861 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
ode-switch.s
|
| da84786bee8304588a4325b15e297be1995a5d41 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 prefer encoding T3 to T4 for ADD/SUB immediate instructions.
rdar://10529348
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145851 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 253ef7a77930f6855a5bf24037e9dfbc65a1ee85 |
05-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for the rest of the VMUL data type aliases.
Finish up rdar://10522016.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145846 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.s
|
| c4f0b309eeaa479de9bbf62eaf304931a526f622 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for VLD1 single lane w/ writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145713 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| dad2f8e7fb2df5fb080a38fa4c33a01f19729f15 |
02-Dec-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up aliases for ARM VLD1 single-lane assembly parsing a bit.
Add the 16-bit lane variants while I'm at it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145693 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| e30171ba0ce10c8a37ee1aabc0d5cd13136dc7c4 |
30-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some tests for all-lanes VLD1 parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145512 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 4c7edb3ad8bd513c59190f6ebee9bee34af7d247 |
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for four-register VST1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| ed1f83f9af83f71b04b2aef820195d8db5dab00a |
29-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable some VST1 tests and add a few more.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| d2bf432b2b6ba02e20958953a237213d48b00f20 |
27-Nov-2011 |
Chris Lattner <sabre@nondot.org> |
Upgrade syntax of tests using volatile instructions to use 'load volatile' instead of 'volatile load', which is archaic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145171 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-01.ll
|
| 9b1671bae7beeef848f19424c42ad161c6eb1082 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove obsolete test.
The PLD encoding is checked via the .s file now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144853 91177308-0d34-0410-b5e6-96231b3b80d8
refetch.ll
|
| 2abba8496cb394af53b531e95067d5cae78bb9ee |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144852 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 47a906ac2376bd6288270f2f6d4e06b5a988bd14 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for r144842.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144851 91177308-0d34-0410-b5e6-96231b3b80d8
op-armv6t2-padding.s
|
| e43862b6a6130ec29ee4e9e6c6c30b5607c9a728 |
16-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for register range syntax for VLD/VST register lists.
For example,
vld1.f64 {d2-d5}, [r2,:128]!
Should be equivalent to:
vld1.f64 {d2,d3,d4,d5}, [r2,:128]!
It's not documented syntax in the ARM ARM, but it is consistent with what's
accepted for VLDM/VSTM and is unambiguous in meaning, so it's a good thing to
support.
rdar://10451128
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144727 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 9f302c4fb3feeb36561a6eee0168ee5242d8ac20 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing two operand forms for shift instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144713 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 19885de61ddbfe1a0db858e303baf19a190bc57a |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM alternate size suffices for VTRN instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144694 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.s
|
| a68e90c36e6a53fb1889b608f44d6244a36b3e97 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns.
Yet more of rdar://10435076.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| bfb0a1717bb140c418e070042e852f925e92de01 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for two-operand form of 'mul' instruction.
rdar://10449856.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| d2586daf069f480e924cd7dd2079dd39de331541 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for two-operand form of 'mul' instruction.
Ongoing rdar://10435114.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144688 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 908f923cfc63c9c941dfa77b13a281f4d845e03c |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcase for r144684.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144685 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 1de0bd194540f8bab399fb39c4ba615a7b2381d3 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing for mul.w in IT block fix.
When the 3rd operand is not a low-register, and the first two operands are
the same low register, the parser was incorrectly trying to use the 16-bit
instruction encoding.
rdar://10449281
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144679 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| dd47e0b5d4850fede4b2581c41f1e0a5eff5f05a |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for non-writeback VST1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| e052b9afa1301419f8b52eed9ed370393fcad78d |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing datatype suffix variants for non-writeback VLD1 instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144592 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| ef448767a35148261d6c82a8e55e6e2f4be8e631 |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing optional datatype suffix for VAND/VEOR/VORR instructions.
rdar://10435076
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144587 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| ffc658b056b7cc0b3f6a2626694b6a4216ed728d |
15-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| c7352f8ca0fc716c38cb3d81e63e943d47d578b3 |
12-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM optional size suffix for VLDR/VSTR syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| ce485e7f70faed6d19daafff91bb20509403d432 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM allow Q registers in vldm/vstm register lists.
rdar://9672822
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 5402637ff283d7397513d5c1699cdf2274c47313 |
11-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing for push/pop w/ hi registers in the reglist.
rdar://10130228.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144331 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 1b332860aef0121cf4591f4377a7201ce0ef8366 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb MUL assembly parsing for 3-operand form.
Get the source register that isn't tied to the destination register correct,
even when the assembly source operand order is backwards.
rdar://10428630
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144322 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| ee10ff89a2934636570cb17b756bf31b2a38aab5 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for LSR/LSL/ROR(immediate).
More of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144301 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
humb-diagnostics.s
|
| 71810ab7c0ecd6927dde1eee0c73169642f3764d |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for ASR(immediate).
Start of rdar://9704684
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144293 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 3c5d6e4df495316c0d2e0a7bca5ec7a88aa400a5 |
10-Nov-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing STMDB w/ optional .w suffix.
rdar://10422955
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144242 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 70be28a5adba5bcae0c6dcd63f17592864c351fc |
07-Nov-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Simplify some uses of utohexstr.
As a side effect hex is printed lowercase instead of uppercase now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144013 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
eon-mov-encoding.s
eont2-mov-encoding.s
|
| 89a633708542de5847e807f98f86edfefc9fc019 |
29-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".
When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example,
mov r2, #-3
becomes
mvn r2, #2
rdar://10349224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143235 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 5d0492cfc4521ccb13b4961227b279991a17c393 |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ADD/SUB instructions encoding selection outside IT block.
Outside an IT block, "add r3, #2" should select a 32-bit wide encoding
rather than generating an error indicating the 16-bit encoding is only
legal in an IT block (outside, the 'S' suffic is required for the 16-bit
encoding).
rdar://10348481
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143201 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
humb-diagnostics.s
|
| c73d73eb881ebe7493e934c00ca1c474ffd0ed2d |
28-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Allow 'q' registers in VLD/VST vector lists.
Just treat it as if the constituent D registers where specified.
rdar://10348896
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143167 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 88484c00307274568ab068909cb38ecaedd41cbf |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.
rdar://10348844
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143110 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 036a67d670413f8116415b87457f22d256f314ae |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.
rdar://10348584
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143108 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| a581328ceb4c9db165d79a4dabd6b28db799d70f |
27-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 ldr pc-relative encoding fixes.
We were parsing label references to the i12 encoding, which isn't right.
They need to go to the pci variant instead.
More of rdar://10348687
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143068 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 399cdca4d201f7232126c3a0643669971ede780a |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 with writeback.
Four entry register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142882 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 5921675ff5ea632ab1e6d7aa5d1f263b858bbafa |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
Three entry register list variation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142876 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 12431329d617064d6e72dd040a58c1635cc261ab |
25-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VLD1 w/ writeback.
One and two length register list variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142861 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 1028132b90a10a46c87b2ee2ad0156e2f9143c25 |
24-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for r142801.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142806 91177308-0d34-0410-b5e6-96231b3b80d8
lf-thumbfunc-reloc.ll
|
| 224180e81b34c99d15e35a4d4de6729357c6d372 |
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142704 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 4661d4cac3ba7f480a91d0ccd35fb2d22d9692d3 |
22-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 2-register sequential variant of VLD2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142691 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| b6310316dbaf8716003531d7ed245f77f1a76a11 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 4-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142682 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| cdcfa280568d5d48ebeba2dcfc87915105e090d1 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Assembly parsing for 3-register variant of VLD1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142675 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 280dfad48940a0a51726308dd3daa3b1b0d18705 |
21-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD parsing and encoding.
Next step in the ongoing saga of NEON load/store assmebly parsing. Handle
VLD1 instructions that take a two-register register list.
Adjust the instruction definitions to only have the single encoded register
as an operand. The super-register from the pseudo is kept as an implicit def,
so passes which come after pseudo-expansion still know that the instruction
defines the other subregs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142670 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| cd20c58e980552daef182247005cf905fe8b06ba |
21-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142626 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 50965031848f391f98f11770b3823497d5bf5c15 |
20-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Fix tests for corrected MSR encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142622 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 6b09c77b7a831f57ccedb20c760031492a0af043 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
eon-vst-encoding.s
|
| 760b46ce1851f9414c4d95093e8897cb32734560 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142582 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| d0b614754eb2d5ce9c2b0841270872129f956059 |
20-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM VTBX (one register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142581 91177308-0d34-0410-b5e6-96231b3b80d8
eon-table-encoding.s
|
| 2933e4b2e65a5c5ae9958d4550cd47db793b9e54 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142422 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-table-encoding.s
|
| 39dc2af7f99c92a0c11f19b8b97bd306c75c3bdd |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142421 91177308-0d34-0410-b5e6-96231b3b80d8
eon-table-encoding.s
|
| 0487e459e06a2ae2b6e9633f17a37027c9e34b8b |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable more encoded immediate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142415 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| ca8d1842cff5cd5866c0d4d46cf736ca9f8718f4 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
More vmov lane testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142414 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mov-encoding.s
|
| aead579017d0f8c43dba3bcb049b1d2576b9f8e3 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmla/vmls assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142413 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-accum-encoding.s
|
| 687656c6300138583f2e8e3cdaff6cfeb6261b7f |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmov assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142412 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.s
|
| 9120088979dbcd20e8643bc8f5b22bc605c7d974 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmla/vmls assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142389 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.s
eont2-mul-accum-encoding.s
|
| e8692ed5a66a4382ee0adca317dd348935426d79 |
18-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Another failing encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142388 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-encoding.s
|
| 82fa5fc7093be4b1180f405c4802150fe830033b |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix NEON mul encoding tests. Wrong file contents previously.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142387 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.s
|
| 0a0374018f1d17d6d2895fb73026e2942ab111ed |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vqdmulh assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142386 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-encoding.s
|
| 37a3ed21c4ed418982805150809b846624b853ea |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove duplicate test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142383 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-encoding.s
|
| 9e7df4ad5b46dbb427499da8d4dfde7460c1c5be |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142382 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-encoding.s
|
| 970f787a7e3929c9cc1c0faabf224d26c1fcd252 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vmul assembly parsing for the lane index operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142381 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-encoding.s
|
| ec11d2a1b86378df0d65819b725e2a6b88acafd4 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142380 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-accum-encoding.s
|
| aff187a19ac60fbcbc220f474112d354e57e72b8 |
18-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Add a few more testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142379 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-accum-encoding.s
|
| de1ff7f5520989bf20ef391c9eb4aa320d865fbd |
18-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Add several FIXME cases for ARM encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142377 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-accum-encoding.s
eont2-mul-encoding.s
|
| 5e3e811bf6d4d3fa9fa1c6abdaa6fd7ee75dddf9 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tests for 142365.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142368 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.s
eont2-mul-accum-encoding.s
|
| 444282461406b45c7770b3161b2e879ec4f64da3 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142367 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.s
|
| f2f5bc60f61acf0490d856ddd09e461bf93c5459 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV.i64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142356 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.s
eont2-mov-encoding.s
|
| 6248a546f23e7ffa84c171dc364b922e28467275 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142321 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.s
eont2-mov-encoding.s
|
| 7c81013c4521ceab3e98d5be1fdcf3853e27e077 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable a few more NEON immediate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142313 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.s
|
| ea46110f57b293844a314aec3b8092adf21ff63f |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV/VMVN/VORR/VBIC.i16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142303 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mov-encoding.s
|
| 0e387b2877e4eebeedfcb26b08253f9c1b946035 |
18-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON "vmov.i8" immediate assembly parsing and encoding.
NEON immediates are "interesting". Start of the work to handle parsing them
in an 'as' compatible manner. Getting the matcher to play nicely with
these and the floating point immediates from VFP is an extra fun wrinkle.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142293 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.s
eont2-mov-encoding.s
|
| 008c8384346ddee44b26f0161757432d3137e7b7 |
14-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Update test for disabling of code/data marker labels in ELF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142003 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-01.ll
|
| c66e7afcf2810a2c1ebf08514eaf45c478e5ff67 |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDC/STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141811 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 9f45754750b03516db23b21021db72b20336ea85 |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding tests for STC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141787 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 9b8f2a0b365ea62a5fef80bbaab3cf0252db2fcf |
12-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for the <option> form of LDC/STC instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141786 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 2bd0118472de352745a2e038245fab4974f7c87e |
11-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for LDC{2}{L}/STC{2}{L} instructions.
Fill out the rest of the encoding information, update to properly mark
the LDC/STC instructions as predicable while the LDC2/STC2 instructions are
not, and adjust the parser accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141721 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 051fee03127ed20a6bbe66389c47edcd969f4cc7 |
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable ARM mode VDUP(scalar) tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141447 91177308-0d34-0410-b5e6-96231b3b80d8
eon-dup-encoding.s
|
| 460a90540b045c102012da2492999557e6840526 |
08-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM NEON assembly parsing and encoding for VDUP(scalar).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141446 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-dup-encoding.s
|
| bee5d2fac867a25272bc8a393f3e4f6f581fe07a |
07-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up tests. Un-XFAIL file and mark individual tests as FIXME instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141321 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-dup-encoding.s
|
| 7abb7956350238f2edbc2d8e5d0dec61f44df2c9 |
06-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix and clean up tests. Un-XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141318 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-absdiff-encoding.s
|
| d6f85098e18ee2869e15c41efdff1252f45fa54f |
06-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix and clean up tests. Un-XFAIL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141316 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-pairwise-encoding.s
|
| 2dbb46a0a09d4a16a6752cfcbe1d55d51e7d2a31 |
05-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Support a valid, but not very useful, encoding of CPSIE where none of the AIF bits are set.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141190 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 2fec6c5ff153786744ba7d0d302b73179731c5e9 |
05-Oct-2011 |
Owen Anderson <resistor@mac.com> |
Teach the MC to output code/data region marker labels in MachO and ELF modes. These are used by disassemblers to provide better disassembly, particularly on targets like ARM Thumb that like to intermingle data in the TEXT segment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141135 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-01.ll
|
| 0ebefdf8345d0bdfcccde4057f3cce1c2dbbda9b |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141123 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| fdf6bb41a4677897e91b181eec849e81a822026c |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL file. Comment out individual failing instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141117 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-bitwise-encoding.s
|
| 20f8eb2fc1d1d45d2645a45fe383f572c98d939d |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141115 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-bitwise-encoding.s
|
| e5c933848a2211f7628b2770a8942d48d5bd4230 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL file. Fix incorrect CHECK lines. General format cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141114 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-bitcount-encoding.s
|
| dc6c93531d2bfa4f5aa6c6ce8163365a4750254e |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL file. Fix incorrect CHECK line. General format cleanup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141113 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-mul-accum-encoding.s
|
| 100902c6da10f909610d408255c8899fa04c6de8 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141111 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.s
|
| 0c0cf47ed54e5fa37f656e1274aa680d88202de1 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL file. Fix incorrect CHECK line.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141110 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.s
|
| 62ea269b9a7d0396d02399bb9a95c5f65ecc552c |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141108 91177308-0d34-0410-b5e6-96231b3b80d8
eon-dup-encoding.s
|
| a02dfe7a6bd25b7e18ed472cbf556208658581fc |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Un-XFAIL the file. Disable only the individual tests that aren't working yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141099 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| 36db6fbe57ce5ce53c233ea5ac0f6d4d5e628531 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141096 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| 3207e6c6b78dfe5299cb47c6d04d3ea76dbd0e6d |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. These tests are covered in the .s file tests now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141047 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 9d39036f62674606565217a10db28171b9594bc7 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMOV immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 68259145d9ac1f8d4e2cc9fc73626254fcc5cf08 |
04-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing/encoding for VCMP/VCMPE.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 5cd5ac6ad455880395e34ac647f1e962a83763a0 |
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for VMRS/FMSTAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| f8bf43ec99d4410c3e351c76f806208d1204129e |
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Update test for 141010.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141022 91177308-0d34-0410-b5e6-96231b3b80d8
humb-diagnostics.s
|
| c82c101147ad680d7db45e75886c9a4e8419a2f0 |
03-Oct-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit. Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141010 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.s
|
| acad68da50581de905a994ed3c6b9c197bcea687 |
28-Sep-2011 |
James Molloy <james.molloy@arm.com> |
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
humb2-mclass.s
|
| 25ddc2bf7ed69f500dd4d3e003004bda28c3dd95 |
28-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140647 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 256e10f96461f6a06c0ff3fe892981f40626791e |
27-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Remove incorrect testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140572 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 4d2a00147d19b17d382644de0d6a1f0d3230e0e4 |
24-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140426 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 61268701931d747fa95e0be8a368101e7f97b83c |
22-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140284 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 50172e77bc3c41320a01776461a0e839d718c297 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Nuke obsolete test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140127 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| ac9c2aa8e1b8ff36934e98287e1733995c5ac20d |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for WFE/WFI/YIELD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140126 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 50f1c37123968b7f57068280483ec78f6ff7973e |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UXTAB/UXTAB16/UXTH/UXTB/UXTB16/UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140125 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 400b624e02216dcbe1ec0c17963caa088b33c57a |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USUB8/USUB16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140120 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 6053cd956fa6c781a4ee05cbc99ab15db3cf3d13 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140119 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 653419fff0420a6c9cfc953c135f1e9dc3420a45 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USAT16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140118 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| a7e5b01fe1156050ac9174a421ecf90911e1949c |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for USAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140117 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ae13ba774083ef328a08290af649b4cd1156b40a |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140114 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| ad7d7444563b628dd723015e9c44692d5b67067e |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQSAD8/USADA8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140113 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 73e019eb12bda5a3dd6165b749dfa08b8b30e477 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQSUB16/UQSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140112 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ab3bf97fe029e3ce6834b54c4c5a647c0b665546 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQASX/UQSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140111 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| d7e2785ea8af746abee99aaef074a610d5ed73d8 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UQADD16/UQADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140110 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 9c6712721c114f8e67b9a6b3cb1dd5d18b4cb435 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140096 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| d5d0e81a4bec76a56a1e7b2326ed12bfcbcab9b9 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UMAAL/UMLAL/UMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140095 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 9546de68aac116cdf6f0af5a2972101acc476e0c |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UHSUB16/UHSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140089 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 6729c48b940df5c141eec6375d14544cdbb2ed3f |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UHASX/UHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140088 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 2c1ef5bac85f3ef002047178490a00c5ea2c7cfc |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UHADD16/UHADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140087 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 6451cbf79f75fde6319cd4dbcb8a48aecac702f4 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UBFX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140086 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 4032eaf98c63b0fb1f2418a1cdc56b72bc76c329 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140085 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 11f23c1a7260a1cb4b4eee20aea09676e15d55c0 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix copy/past-o. Gotta remember that 'modify' step...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140082 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 661daa481ef438ea797b01df470d2190c93c9863 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for UADD16/UADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140081 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| aa70695ef045a54eb8c4f701f9db03179c816b48 |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140080 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 7f739bee261debdf56bd89ac922b57eca53e91dc |
20-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TBB/TBH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140078 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 1494c496e2827f991f75eae4acf8f7bf9952abdd |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for TEQ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140070 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 30b8b970e319b92300a9501f4578cb099e29a920 |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove FIXME. TBB/TBH are Thumb mode only instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140048 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 326efe58918d3f0a431d07938054870fcd0e240f |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTB/SXTB16/SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140047 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
iagnostics.s
|
| 8a8d28b0392a27ff8e0c60c04561671023a08dc2 |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SXTAB/SXTAB16/SXTAH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140029 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 9883acd2a6c0851b9095409bcc0541b26165015a |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140025 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 7649b0b8c708f95e318296bd6a4b3968cd6bb38c |
19-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SUB(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140024 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| f67e8554bf4808ad447ffb5d2deebbb10b810391 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SUB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139966 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 47313df81c096005dbbe8dbe729375f7d0bb3e15 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139963 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 18ceae2a705cd4da38a6f67bf0bb9d8615a8b254 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRHT/STRHT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139962 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 4a1d200c2f850dc7b0eda6b8fa89157d21b731c5 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STREX/STREXB/STREXH/STREXD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139961 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| e45451eea9cd7fc78227fdb94f215ff22e9d0f75 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139960 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 75d74282759293b5f5abeae5b3f9e0cec42ae52f |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Simplify comment. There's no Thumb LDRD(register) encoding. That's ARM only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139959 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| e041af7e0e0b6b59457c3218e6489412793a869c |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139957 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| c71ed786c3b7d2e8072483805434e23f77f606c5 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139956 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 59c50760941742870786ca6f497f3dcecfc965e0 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove test of undocumented format.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139955 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 76ca6d9bcd093ced4277109e6819d49eead0c956 |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139954 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 2e7a94137b742798df9678bff925f17844c1e0ca |
17-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle a few more thumb2 tests to match the comment headings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139952 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 5320b40d9e6f9d0cbabcebaa3f224e8ba1fc00cd |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 tests for STR(literal), STR(register) and STR pre/post indexed immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139951 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 0bb7c6e8d627edb8c83599c88ad9315636434418 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle a few tests around.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139950 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 642caea2c624aaeb492a112d60f419ee4d1a10c7 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STR(immediate).
Add aliases for STRB/STRH while there. Tests forthcoming for those.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139942 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 36343d85cd42c5fbeb7556655b9ab48bce8b8fdc |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STMDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139940 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 8213c96655e955a0b63b05580bc2f6a55be26083 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for STMIA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139938 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 3335029b1f4cd663411277aa2f93b4eaa7a0289e |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSUB16/SSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139931 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 50bd470d85c63860f887b7c3e5724c9fd43ef3a2 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139929 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 9f4ddb3efa0f76d7c2463648eca9d82403c2e8a3 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAT16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139927 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| b105b997a49c809bfd464ae7691d5ee45d34f446 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SSAT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139926 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 05ec8f7ac90179cccb476512c872db95bfec418d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SRS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139925 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| dea84127840ad38100569d2cc5045c5086ee668d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMUSD/SMUSDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139923 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 41ca75bed0e32d4ba4fafd445e6641b34e490046 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMULWB/SMULWT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139922 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 3443ed525a3bce98bacabb5aa8e67bee6def3b09 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMULL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139921 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 3c4c879695eb282f01d89da87d5da0a141e7f6f8 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139919 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| d727148c21f7294032a07f7e66b4aa06085c7f0b |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMULBB/SMULBT/SMULTB/SMULTT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139918 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| c9592cbad501956c71cd9e7f515f48e2b05b6052 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMUAD'dib.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139917 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| f3578a84974e0291582966e4a3aebf3802ab211b |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMUL/SMMULR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139916 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| cb574bb71edcb816509db434d220e9e1bb51d53d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMLS/SMMLSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139911 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 3b61d23297a8401fb1aadf129fdfa282f175f88d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMMLA/SMMLAR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139910 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 7ff2472b8235d8702bd04bf297d573d06cf6b40d |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLSLD/SMLSLDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139909 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 920ad2b6810e008ad98ee42b51abf791101aa8df |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLSD/SMLSDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139908 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| f566ca741885285d565ad5347baf9663ed7b7d62 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLAWB/SMLAWT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139907 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 231948f860df79b7f0926305caa065a64d758265 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLALD/SMLALDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139906 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 4f2999b2969416aefe9328b73a61f5d64e424a92 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLALBB/SMLALBT/SMLALTB/SMLALTT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139905 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 837fc5e9d5138ed48a74a672dc4c1525e5975ce8 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLAL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139902 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| e74711b8b0c7abd0383ebb70941cdcb779918e12 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLAD/SMLADX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139884 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 246ae02bce7afb0411d21803eb0ad1b3832189f9 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SMLABB/SMLABT/SMLATB/SMLATT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139881 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| f08084ba4bbabd1c22ad654347e77218a16b9a80 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SHSUB16/SHSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139880 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 5a6370ff99013ce8a9db12e127770395e81767b4 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SHADD16/SHADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139871 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| c075d45364190dfe06eda8aa93b6856d4f55f107 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SHASX/SHSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139870 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| d16160f18af7735924ad37e69f54308ba037f1e9 |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SEV.W.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139866 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 56019a32bdfc65b3e97aec3827f4d12b091365bb |
16-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SEL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139861 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 7ecedac8b726926cce5758b791c5e78caff8b5ad |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SBFX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139858 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 356c759908e1c6b968293d54bc4aa26bc8415407 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some missing 'CHECK' lines and tidy up others.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139849 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb2-instructions.s
|
| fd8b8519087d19d3ac4c3a0b23e6f7a6c2ced46b |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SBC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139844 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| e4e4a93e9ec6040b6466bf067d5e02533471f093 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139843 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ed15ab1aadea6216b30ccfc659b194d09f44ca14 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for SADD16/SADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139841 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 191d33fd6d0a91e89f2a8f719e5adbdccf9effa9 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for RSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139839 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| aba8015cc375ac7de757d92e55d1aad986de6202 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for RRX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139831 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 5260be1f2d8a2efe9aea398248736556cab42eeb |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ROR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139830 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 689b86ed2e1f1daf9201f0ef83ff3bc1d5167232 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for REV16/REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139828 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 1b69a128d6b98456c666b4031cc46c3d0fbe6177 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for REV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139813 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 4bab3c77102954380c923505c413a2df7aca48eb |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for RBIT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139811 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 3e3a9c796453afed58e27d7bab926061f8dd2d16 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for signed saturating arithmetic insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139810 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 07d7f3d387739b52f0fccd7c9d7bb54b0195f56c |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Re-order test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139795 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| f18544d1e55f6e8e3929c1bb840d8fb8709064d0 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for PLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139757 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| f83e297cd1c36293d8950106b6d87f0558f21e80 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for PLD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139756 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 0b69247b10ddbce5f0c476c3471918ffc6091ac5 |
15-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for PKH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139754 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 8adf62034a874adacff158e8adc9438cb3e67c01 |
15-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix a crasher in Thumb2 MOV-immediate encoding for certain inputs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139747 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 0b3ed6de80734c3ac15e1b1f0b5306a1f61f88ce |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139742 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| b72504b4fad51941523b5e6db3edba58a2ebbd90 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ORN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139741 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 5c5eca3534b616fbdb8d2c7c56ab2182f4a9ef05 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for NOP.W.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139740 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
humb2.s
|
| d32872f9ca446fc48084082fcb88255a55405cc2 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139739 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 64944f48a1164c02c15ca423a53919682a89074c |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139735 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| bf841cf3360558d2939c9f1a244a7a7296f846df |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MSR/MRS.
Fix a bug in handling default flags for both ARM and Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139721 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb2-instructions.s
|
| 97f50f3870fabfc7358543699fe608c59c61c2e6 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MRC/MRC2/MRRC/MRRC2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139717 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
humb2-diagnostics.s
|
| 95be01a56905d15f42ca47b793c1af8a5638c89e |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MOVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139715 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| c2d3164ab467bdfa8508b93177e69b99626cd8e2 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing for MOV in IT block.
Select the right 16 vs. 32 bit encoding in an IT block.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139714 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| d0588e2a2ed1f7570f13b78c2042855dc4afae10 |
14-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM fix assembly parser handling of ranges in register lists.
Clean up register list handling in general a bit to explicitly check things
like all the registers being from the same register class.
rdar://8883573
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139707 91177308-0d34-0410-b5e6-96231b3b80d8
iagnostics.s
eg-list.s
|
| b6b7f515e2b90c9f9b6cdd5b9648121f6ad2b3a1 |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Teach the Thumb ASM parser that BKPT is allowed in IT blocks, even though it is always executed unconditionally.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139610 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 12c7e90d369b4605aac0ddbd252231beacb2aabb |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb2 shifted register operands with RRX shifts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139606 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 926785487d95e4b0afef2c375a06b41dd317e836 |
13-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix a failing ELF Thumb test. I _think_ this is right, but it's not totally clear to me what this test is doing. Could someone on an ELF platform check?
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139549 91177308-0d34-0410-b5e6-96231b3b80d8
lf-thumbfunc-reloc.ll
|
| fd92d2e106acfbf13ed29b5d15f3a690cd8699b2 |
12-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative LDRSHW with an immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139537 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 1ad60c2adc9ed765a968747d0c548cda53bfd384 |
10-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for MOV(immediate).
Some aliases for MOV(register) also to keep existing T1 tests happy when
run in thumbv7 mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139440 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 08fef885eb39339a47e3be7f0842b1db33683003 |
10-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139422 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 51f6a7abf27fc92c3d8904c2334feab8b498e8e9 |
09-Sep-2011 |
Owen Anderson <resistor@mac.com> |
Thumb unconditional branches are allowed in IT blocks, and therefore should have a predicate operand, unlike conditional branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139415 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 468709e43dfff52f48af9ff411d461e22b6e2015 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MLA and MLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139399 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 84d043a8b38d43a16549ca7e7cc9b275b2fa3aea |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for MCR, MCR2, MCRR, MCRR2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139397 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 1e0fff17f3182a2bef5e06cca996a8d16e53cb46 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139396 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 95102265a96104512abbf0d8e316a1ef8473b994 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LSL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139395 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| d4b72de3e2c9bd2397f37272c0904c53036e38d4 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139393 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 56806c29973a801a8311b5501c05a0a49651b42f |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSHT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139392 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| a315a9909387cdf8ce36077d7aa91844caa2f19d |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139391 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 578edfbfa072a82ce22790567d3db434710e7551 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139390 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 0811fe13d65c67e4c22d9113795deabbd0daa277 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139389 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 95d397c3b1e5001e5b25b04c52c13a19ec379c2f |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139386 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 1efd9a0e8b01abf3b3d7048a80c08599f7d3eefd |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139385 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| b6aed508e310e31dcb080e761ca856127cec0773 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDREX/LDREXB/LDREXD/LDREXH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139381 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| e3a0adf162a849c7dd01514d151651850451db38 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139371 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| a77295db19527503d6b290e4f34f273d0a789365 |
09-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRD(immediate).
Refactor operand handling for STRD as well. Tests for that forthcoming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139322 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 9ea33b0c03e5c0a66b9d8385e164362b186513b1 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for Thumb2 LDRB indexed addressing w/ writeback.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139292 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| e64fb28da191bc978ab99ea397e6108a15c364f8 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR post-indexed.
More cleanup of the general indexed addressing T2 instructions. Still more to
do, especially for stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139272 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| eeec025cf5a2236ee9527a3312496a6ea42100c6 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR pre-indexed w/ writeback.
Adjust encoding of writeback load/store instructions to better reflect the
way the operand types are represented.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139270 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| f0eee6eca8c39b11b6a41d9b04eba8985655df77 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRBT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139267 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 489c693f65521649dbee0378dbb465029d71c712 |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRB(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139266 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ab899c1bcca7f1cc85342c3a686464ba4af035df |
08-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139264 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 8bb5a861a0efae6b9c8f07936ad9bb3508ada23e |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDRB(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139258 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 1aedfb47f96a396e8364ec41c94ee75db84d769e |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for LDR(literal).
Need branch relocation support to distinguish this encoding from the
16-bit Thumb1 encoding w/o the explicit .w suffix. That comes later, though.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139257 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ed1cb6defa02d92302288410c35464c764adb060 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for Thumb2 LDR(immediate) from r139254.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139255 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 94f914e3fd4b040edd81abb5f455ed2b99e2572a |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDMDB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139251 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 76ecc3d35b4d16afb016bb14e29e12802b968716 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for LDMIA.
Choose 32-bit vs. 16-bit encoding when there's no .w suffix in post-processing
as match classes are insufficient to handle the context-sensitiveness of
the writeback operand's legality for the 16-bit encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139242 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| aa833e53dc74db6cb6789ef7f05c620d28980983 |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ISB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139200 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 8f6d8104fc20550da00c3a4a0bc66de64117826d |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for EOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139199 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 94d1c489a5f75f6092de413f7891449008ed91fd |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139194 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 06c1a51241852bd652ae6473afaa71d96d48b0eb |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DMB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139193 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 77951908b76c00315f1a74d09fb45530029638ec |
07-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for DBG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139191 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ef88a926778b15aa4527a148a514ed0585af7cb1 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CMN and CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139188 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 0b533a3bd39471d6dce5a4495f25323a0bb515e0 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CLZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139177 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ad2dad930d450d721209531175b0cbfdc8402558 |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CLREX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139172 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 79d56a66c3d763b3a8147581c75c184cd48abcdc |
06-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CDP/CDP2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139168 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 83452b206459f56454443b4caffa2e5bf1422def |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for CBZ/CBNZ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139054 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 6c3e11ea55172def6f9829cc24cc5c3b071208ba |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BXJ.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139053 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| cefd2020a671248b3266bc2e818645db98f3a1d9 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139052 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 0b9a3d37c5a6c452b40beede7519be97cad97ef0 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BFI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139051 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 7413f41d3b45d9fe851943d110a5ef5a54a5e076 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for BFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139050 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| a110988b391652e3f4f85cb709a3eeb81c8cdd84 |
03-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding of B instruction.
Tweak handling of IT blocks a bit to enable this. The differentiation between
B and Bcc needs special sauce.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139049 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 5f25fb01b4061725124e34a942809e9c0c6f681c |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ASR.
For other shift and rotate instructions, too. Tests for those forthcoming
as I work my way through the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139040 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 5c1ac5554229d5481b772cb017139bdd24d5114d |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for AND (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139021 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| f0851e5d95a1d1f746a3b1e9633af76496e316e7 |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ADD (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139017 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| ca52a7e38c0bcdd1a8f32212239606fe1f5e3152 |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Tests for Thumb2 AND (immediate) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139013 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
humb2.s
|
| aca878c5e6d8ed34e436f4a4ec3b4e4dff3616db |
02-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME. Thumb2 ADR encoding choice is non-trivial.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139008 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 2f25d9b9334662e846460e98a8fe2dae4f233068 |
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM 'rscs' mnemonic is carry-setting 'rsc', not 'rs' with a 'cs' condition code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138952 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 7f17b5a483ea358f2b9e3958f16cf34d75d5b4da |
01-Sep-2011 |
Owen Anderson <resistor@mac.com> |
t2Bcc is allowed to have a predicate without a preceding IT instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138946 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 20ed2e7939d6a8e804a51897c3af4588deb48be2 |
01-Sep-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding for ADD(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138922 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
humb-diagnostics.s
|
| 721cb1fde07423fd1905338d443172a8028ad634 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding for tBcc with immediate offset operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138889 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| e0e42bf0bb1280a881450027aaae6490b4c87fd5 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Run the Thumb1 parser tests in Thumb2 mode, as well.
Thumb2 is a superset of Thumb1, so all of the encodings should still work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138883 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| d82175c1f03e6a83b4dbe53f884f72a2441d5c34 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb NOP encoding varies depending on ARCH revision.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138876 91177308-0d34-0410-b5e6-96231b3b80d8
humb-nop.s
|
| 559c277aa9242dd5b32d2f2ccc353d938f886ee9 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix roundtripping of Thumb BL/BLX instructions with immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138874 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 72335d55d972dd7279fe68ed05fa3c4e7fce9345 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for ADC(register).
Also add instruction aliases for non-.w versions of SBC since they're the
same.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138871 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 0f3abd8d68cfb4a0705d0a8140d7f7dce32f6e77 |
31-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak Thumb1 ADD encoding selection a bit.
When the destination register of an add immediate instruction is
explicitly specified, encoding T1 is preferred, else encoding T2 is
preferred.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138862 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 21df36c57afc588c8073a070a47e3ba45fa87270 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather than labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138837 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| a7710edd98d71a81c43f8e3889cf0c790885d1b8 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets instead of labels.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138835 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 391ac65377f2ad5e48a796e75120959e22430605 |
31-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb1 B instructions with immediate offsets, which is necessary for round-tripping.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138834 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 694e0ffb8aa3a8651003e448135aba0e663782bd |
30-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add missing encoding information for some of the GPR<->FP register moves.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| abd3f6085998e7479cf474d7352c6e1394bcbb68 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove redundant tests from XFAIL'ed test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138779 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| a01e12499f0e9dd0c5dec0650e817a009cdd1238 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 assembly parsing and encoding support for ADC(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138778 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
|
| 056cb4c0f63fc7bdb5d5378baec2efeb95efc0b6 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove test file. Superceded by other more exhaustive tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138777 91177308-0d34-0410-b5e6-96231b3b80d8
humb2_instructions.s
|
| f8e1e3e729473b8b2b7ee6134b6417976af84d05 |
30-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb2 parsing and encoding for IT blocks.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138773 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb2-instructions.s
humb2-diagnostics.s
|
| 0da10cf44d0f22111dae728bb535ade2283d976b |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve handling of #-0 offsets for many more pre-indexed addressing modes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
imple-fp-encoding.s
|
| 63553c77cd1cf3b204d955fb65350db087aaff1d |
29-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Add support for parsing #-0 on non-memory-operand immediate values, and add a testcase that necessitates it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138739 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| f1eab597b2316c6cfcabfcee98895fedb2071722 |
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Improve encoding support for BLX with immediat eoperands, and fix a BLX decoding bug this uncovered.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138675 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| d7568e1c355f5e364eddafc15c6d5553559f32a5 |
27-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Correct encoding of BL with immediate offset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138673 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 96425c846494c1c20a4c931f4783571295ab170c |
26-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Support an extension of ARM asm syntax to allow immediate operands to ADR instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138635 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
asic-thumb-instructions.s
|
| 070260cb29ca9024d4fa1d3aabd6c8320b747f5e |
25-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Update tests for 138501.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138502 91177308-0d34-0410-b5e6-96231b3b80d8
lf-thumbfunc-reloc.ll
|
| f69c80403620ef38674e037ae2664f1bbe5a4f3c |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SUB (SP minu immediate).
Fix FiXME in test file. Remove FIXME for SUB (SP minus register) since that
form is Thumb2 only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138494 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 72f39f8436848885176943b0ba985a7171145423 |
24-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for ADD SP instructions.
Fix the test FIXME and add parsing support for the ADD (SP plus immediate)
and ADD (SP plus register) instruction forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138488 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 99e84e07ff94f24fdbd05f21d4cf5afb822542fe |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for WFE, WFI and YIELD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138364 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 3284db5bfbd313da3492bcae36cbe7305071c05c |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for UXTB and UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138363 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 010bebc696156eb4fe346c0d3566fb855ddfc937 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for TST.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138362 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 4b6658dd0a15fc81f117e672ed1eb72720615d13 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SXTB and SXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138361 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| ec8b866434d530dee5b885e9db8da86db053c9ff |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SVC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138360 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 414b02357a7a733e3258da1b7c0f2c12b32f193e |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SUB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138359 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 743c0fa7791c1451016a469bb0a5f57d56cd986a |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138352 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| aec3a61c8b3fb3fbcafcc493ef38a37e39f039ab |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138349 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 803b1aa8ef00698de62181b9205cfcc0ce6b0ceb |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138348 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 4c821d800a50251633c206b9fe42c99e12f3f511 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STR.
Not including tSTRspi.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138347 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 1e84f19337d44c04e74af4fb005550b525ef60e5 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138345 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 7e99b5c8a36e3e8d611e47122f9c596b58ccf3e8 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SETEND.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138312 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 04d55f1905748b0d66655e2332e1a232a3f665f4 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for SBC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138311 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 934755ac040c516eac7fdd974e87590543acd16a |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for RSB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138308 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 3f57a9a2cf375fe54c274e1e52e2b743d452ffac |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for ROR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138304 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| ab585e61464f4b1bcbc01d61d08a7d87c227997d |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for REV/REV16/REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138303 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 6dcafc0d0b33bebcac28539257a9a5b250542f6a |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve error checking for tPUSH and tPOP register lists.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138295 91177308-0d34-0410-b5e6-96231b3b80d8
humb-diagnostics.s
|
| 762f70bc49b75fa64a79b4ec87e474253418a5a1 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up. Trailing whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138293 91177308-0d34-0410-b5e6-96231b3b80d8
eg-list.s
|
| 0c2165bbd096d49c17562c2951cecca582e01c75 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding for PUSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138290 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 10fd9ad8f33815cdbdc0e2db5860f9c5b1954040 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix think-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138288 91177308-0d34-0410-b5e6-96231b3b80d8
humb-diagnostics.s
|
| 7260c6a4ea19f5eb94068296c1c8e01a99f17a01 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assemmbly parsing diagnostic improvements for LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138287 91177308-0d34-0410-b5e6-96231b3b80d8
humb-diagnostics.s
|
| d937d951256372a24eb6ac9f048816b0873ed528 |
23-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for POP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138286 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 011af5ca801cb95117a9abe2b217f78e2a7c8899 |
22-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ORR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138245 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 0780b6303b99441fef04340b7a083006484f4743 |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing and encoding support for NOP.
The irony is not lost that this is not a completely trivial patchset.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138143 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb.s
|
| 2c3f70e5d4b4f179f21ed1b2ba14674f9d65c9b0 |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for NEG.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138131 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 7a010694209ce46c4f415c0b42c3bc03dc094a5c |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Be more lenient on tied operand matching for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138124 91177308-0d34-0410-b5e6-96231b3b80d8
humb-diagnostics.s
|
| c4762a9c912802ef6e81b722ccb7417f259bb49d |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MVN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138109 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 88ae2bc6d53bbf58422ff74729da18a53e155b4a |
20-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138108 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 584fb0e6635535130ce321d5af15530a7c2ff05a |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138077 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 4ec6e888ec6d12b5255afd685b05c8fee1f7fc73 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138076 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| c7ebca335d841247721128b75f0bc2b98ad6acc0 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138065 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 560ef9f2fe5f0fe0f8603ab3d076dae088efa6de |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LSL(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138064 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 1b7b68f08776dc9553399dc3b4e7ab54e5e596c0 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LSL(immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138063 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 05b01567349dc6c98f9e68c1d4a639aca7ad5ac4 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRSB and LDRSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138061 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 38466309d5c8ce408f05567fa47aeaa3b5826080 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138060 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 48ff5ffe9e2a90f853ce3645b1b97ea7885eccf1 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDRB.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138059 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 09f6e0dfda121251c5da7dba04b8b72d5572b0df |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138056 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 67b95f902a51b591b6178e370d23ffaca841275d |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(literal).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138052 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| ecd858968384be029574d845eb098d357049e02e |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(immediate) form T2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138050 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 60f91a3d9518617e29da18477ae433b8f0069304 |
19-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDR(immediate) form T1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138047 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 93b3eff62322803a520e183fdc294bffd6d99bfa |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for LDM instruction.
Fix base register type and canonicallize to the "ldm" spelling rather than
"ldmia." Add diagnostics for incorrect writeback token and out-of-range
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137986 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 1eba8a66b62e74cc560949ccb0fd9b8af7276aea |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for EOR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137964 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 0d1511c022e78e6d8769290b451b98a3b656de63 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137963 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 7750b8df6aaf9182b8205b98c335bf0f0b19e1b6 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding test for CMN.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137957 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 6ea80e964ba0f8a3420b10bf21172508f713fafc |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BX/BLX (register).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137949 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| ded439886aa0a96df55820e6f84342210660e0f4 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BL/BLX (immediate).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137948 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 37f88c7812e4c284bde325e5af583889b6a80fc5 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BKPT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137898 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 5b657de62ba6e7a7dd873b7a5d10e146b3e35f53 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding test for BIC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137895 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 395b453bed53a60c559b679eb92f75d0b140b307 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for B.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137891 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 00f5d982057574cf65a4a3f29548ff9fb0ecfbd0 |
18-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ASR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137889 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
humb-diagnostics.s
|
| 5a1cd045cd4220f84dae81ab2079e2272dfc51c1 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ADR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137864 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 53727fc659af5f8fc51499fd875165533187d734 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add a couple of FIXMEs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137861 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 358499ea3b72dda4392d340ee5a36d1bbe76728c |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ADC(register) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137833 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| b1ee18ee69624d51211e59fa42b54a0f5827318a |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add missing '@' delimiter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137832 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 89e2aa6afd408f1b4c6b47c53bbf31d48463bcab |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb ADD(immediate) parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137788 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| 194bd8982936c819a4b14335a4d08f28af8f3d42 |
17-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb parsing diagnostics for low-reg requirements on ADD and MOV.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137779 91177308-0d34-0410-b5e6-96231b3b80d8
humb-diagnostics.s
|
| 3912b73c74dc9c928228504e9a23c577b57c4e12 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Thumb assembly parsing and encoding for ADD(register) instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137759 91177308-0d34-0410-b5e6-96231b3b80d8
asic-thumb-instructions.s
|
| c2408d3ce5fcd1fd4861772fdbe3b6447836e254 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add testcase for r137746.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137754 91177308-0d34-0410-b5e6-96231b3b80d8
humb-diagnostics.s
|
| be2ac8ca7bc02f9139c6f8de1ab1db3df743d969 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137747 91177308-0d34-0410-b5e6-96231b3b80d8
ode-switch.s
|
| 47a0d52b69056250a1edaca8b28f705993094542 |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM thumb assembly parsing for arithmetic flag setting instructions.
Thumb one requires that many arithmetic instruction forms have an 'S'
suffix. For Thumb2, the whether the suffix is required or precluded depends
on whether the instruction is in an IT block. Use target parser predicates
to check for these sorts of context-sensitive constraints.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137746 91177308-0d34-0410-b5e6-96231b3b80d8
ode-switch.s
op-thumb-padding.s
op-thumb2-padding.s
|
| d0d3f7e01ff7f83575816f6e1d75aa2224ebc2cb |
16-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM .align NOP padding uses different encoding pre-ARMv6.
Patch by Kristof Beyls and James Malloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137723 91177308-0d34-0410-b5e6-96231b3b80d8
op-armv4-padding.s
op-armv6t2-padding.s
op-thumb-padding.s
op-thumb2-padding.s
|
| 5df7ef6cdbdaaa6bf3bf12b959557a44fbf250a6 |
15-Aug-2011 |
Owen Anderson <resistor@mac.com> |
Fix incorrect encoding of UMAAL and friends. Patch by James Molloy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137641 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 7a8729effc8e6f825cb87e0f95e25b1861bebc1f |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137471 91177308-0d34-0410-b5e6-96231b3b80d8
eon-dup-encoding.s
|
| 46c38aff89c36a95bc9e61c6133056a5de9e5e59 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Tidy up formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137464 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| 29e7b7deb4d582926299c9e69d59e7be45e6ef75 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up formatting a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137393 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.s
|
| 857e1a7b3fcc848a6508f9205f22e8e0d293dcae |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM vector compare to zero instruction assembly parsing support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137389 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.s
|
| c69c26d95e4dcffb3ab98c49f3672386b401d0f9 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix tests per now-correct encoding as of r137371.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137376 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 342ebd5f380637d965504dcc350f9d0d79bbe599 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137372 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode2.s
|
| dd32ba337aab88c215108ca8bf4a0267fce1e773 |
12-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load shifted register pre-index fix shift value asm parser encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137367 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 2ef8241ce7898d49f882e2124064ea953bf9f512 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137358 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 7b8f46cf9e31d730acc25be771462e2a6a1a1dfb |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137353 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 14605d1a679d55ff25875656e100ff455194ee17 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRD assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137342 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 10348e70d567fb61f6c762d99e91e215c720ebd1 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137337 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 961afdf1b641cfa9ed66a6705046393e1dea8847 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137336 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 534de6cad8654af30982edde7dc59d9472a6d2f6 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STRB assembly parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137335 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| c15bd92d2f4beba90b991d10f6df2f74f8cd8f1e |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix a copy/paste error so that LDRB(register) actually gets tested.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137333 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| f91c14920c8cb66195380b5f83e8a98852bedd6a |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR(register) assembly parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137332 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 548340c4bfa596b602f286dfd3a8782817859d95 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM STR(immediate) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137331 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
asic-arm-instructions.s
|
| f6713916fb4504aab617f0e317689acd878cc37f |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM push of a single register encodes as pre-indexed STR.
Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137318 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| f8fce711e8b756adca63044f7d122648c960ab96 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM pop of a single register encodes as post-indexed LDR.
Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137316 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 64104f48f23ff46538e46f01c076fef2ff55d97f |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137274 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| e0109c07ff2861cbfbcbcd0ff69acd420c82ca9f |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSH assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137272 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 7d179b59cd7ae2594ef9f25e0b8369ad98f97386 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSBT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137271 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 5e921594007c4f8b587b8bf15825af0fe8998497 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRSB assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137270 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 263bb07135bc34982fca7efc7c4ed56abee21281 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137265 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| de2f526c7cb2acd0447b59f3def40d35c8bc80f7 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRHT assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137263 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 46b355479f6e2da25bde2df09874c5da690ddd3c |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for LDRH(register) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137261 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 623a454b0f5c300e69a19984d7855a1e976c3d09 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRH(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137260 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| c7de52fcff2d8021fcd68c97cdbf2010b7068e47 |
11-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137258 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 251bf25e7ee9702fed2a66deeb404ce473f7bac1 |
10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(register) assembly parsing and encoding.
Add support for literal encoding of #-0 along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137254 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 2fd2b87ded53f6b87eb240c17d62a23fb4964ba0 |
10-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM LDRD(immediate) assembly parsing and encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137244 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
iagnostics.s
|
| 3148a654909e55e8511a1c23991bf0ae8d3f9204 |
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for LDRBT instruction.
Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137074 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| bc6fc20fcc94d5492a5e5604137a46fd9cffb040 |
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for LDRB instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137071 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 8668a5b0c86ba070176a76accfd48586c0442399 |
09-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137070 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 0d6fac36eda6b65f0e396b24c5bce582f89f7992 |
06-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM load instruction shifted register index operands.
Parsing and encoding for shifted index operands for load instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136986 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| f4fa3d6e463e88743983ccfa027a7555a8720917 |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM indexed load assembly parsing and encoding.
More parsing support for indexed loads. Fix pre-indexed with writeback
parsing for register offsets and handle basic post-indexed offsets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136982 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 6fc1c08635a6bdd6caea234b756f0dd62581e73c |
05-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
Add ARM LDR parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136977 91177308-0d34-0410-b5e6-96231b3b80d8
rm-memory-instructions.s
|
| 71a8f5ca12e8536e6050cc7a09fa2a87ea629cfa |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
print st_type with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136875 91177308-0d34-0410-b5e6-96231b3b80d8
lf-thumbfunc.s
|
| d7c278326f333f41d8ec8d19f817a117e3f11190 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Print st_bind with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136874 91177308-0d34-0410-b5e6-96231b3b80d8
lf-thumbfunc.s
|
| a83f8ef9b4d727011ee43743810ef1f6ec12bb81 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Print r_sym with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136873 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-01.ll
lf-reloc-02.ll
lf-reloc-03.ll
lf-thumbfunc-reloc.ll
|
| f81f6758f3188e1fd8be6b3707301959268dbbf0 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Print r_type with the correct number of bits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136872 91177308-0d34-0410-b5e6-96231b3b80d8
lf-movt.s
lf-reloc-01.ll
lf-reloc-02.ll
lf-reloc-03.ll
lf-thumbfunc-reloc.ll
|
| 65ad8dc807174b53615181a8170befdf60b6771d |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Another counter goes decimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136871 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-01.ll
lf-reloc-02.ll
lf-reloc-03.ll
lf-thumbfunc-reloc.ll
lf-thumbfunc.s
|
| f7179de2a5c127d08e6d24e507abec516f2fc597 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Change anther counter to decimal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136870 91177308-0d34-0410-b5e6-96231b3b80d8
lf-movt.s
lf-reloc-01.ll
lf-reloc-02.ll
lf-reloc-03.ll
lf-thumbfunc-reloc.ll
|
| 014180d387a875f7e04fd3532eab24dd0794db08 |
04-Aug-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't print a counter in hex.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136869 91177308-0d34-0410-b5e6-96231b3b80d8
scale-attributes.ll
|
| 7ce057983ea7b8ad42d5cca1bb5d3f6941662269 |
04-Aug-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM refactoring assembly parsing of memory address operands.
Memory operand parsing is a bit haphazzard at the moment, in no small part
due to the even more haphazzard representations of memory operands in the .td
files. Start cleaning that all up, at least a bit.
The addressing modes in the .td files will be being simplified to not be
so monolithic, especially with regards to immediate vs. register offsets
and post-indexed addressing. addrmode3 is on its way with this patch, for
example.
This patch is foundational to enable going back to smaller incremental patches
for the individual memory referencing instructions themselves. It does just
enough to get the basics in place and handle the "make check" regression tests
we already have.
Follow-up work will be fleshing out the details and adding more robust test
cases for the individual instructions, starting with ARM mode and moving from
there into Thumb and Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136845 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode3.s
humb2_instructions.s
|
| e1cf5902ec832cecdd5a94b9701930253d410741 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM SRS instruction parsing, diassembly and encoding support.
Fix the instruction encoding for operands. Refactor mode to use explicit
instruction definitions per FIXME to be more consistent with loads/stores.
Fix disassembler accordingly. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136509 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 2c6363a62df95b74468d9a561bbcb9edddeb3507 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for RFE instruction.
Fill in the missing fixed bits and the register operand bits of the instruction
encoding. Refactor the definition to make the mode explicit, which is
consistent with how loads and stores are normally represented and makes
parsing much easier. Add parsing aliases for pseudo-instruction variants.
Update the disassembler for the new representations. Add tests for parsing and
encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136479 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 71d3d67508176091575714dddf008b77db4089c9 |
29-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM update tests for CPS instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136472 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| c5b3c58ae8f954587bbb651dec7990744a29f12d |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
CBZ/CBNZ are Thumb2 only. No need for ARM mode tests for them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136408 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| cf121c35c484ee17210fde1cecbd896348cd654a |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for BLX (immediate).
Add parsing support for BLX (immediate). Since the register operand version is
predicated and the label operand version is not, we have to use some special
handling to get the operand list right for matching.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136406 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 43afb6ff1cf7b040e2d70abb47679e1357a329d5 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove obsolete FIXME reference in comment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136400 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 293a2ee3063953bb6f5bc828831f985f054782a3 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for BFC and BFI.
Add parsing support that handles converting the lsb+width source into the
odd way we represent the instruction (an inverted bitfield mask).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136399 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 70a0915cd135b48c557a5bc81b37e33f54fe150e |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for ADR.
The label does not have a '#' prefix. Add parsing and encoding tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136360 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 19b9d6912ab4d61666d5eed0a9c7d407d564ce1d |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM tests for parsing and encoding of WFE, WFI and YIELD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136358 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 8050a619145f30cdfee9c6ae1c5bdb1a32a4a71e |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests.
UXTAB, UXTAB16, UXTAH, UXTB, UXTB16, and UXTH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136312 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| ed398468b51c6eb5b2c9a5bccc8669854cf589a8 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for USUB16 and USUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136289 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 953e2e81dec27fe40315100714eb15c967a9fc1e |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for USAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136288 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| fc2eb31a3c054f9611a2e88238fbb5a8842064a6 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Clean up tabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136286 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| addec77b54fd77e99fd01f462a3fb8c3c89066fa |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding support for USAT and USAT16.
Use range checked immediate operands for instructions. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136285 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 5f33d13da41f55e7421eee3bbfa410d07bd7af19 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for USAD8 and USADA8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136284 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 144da2c8f03834e76ddb617498be7ed864a5c192 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQSUB16 and UQSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136282 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 41438398c13be01ec53c3ad6b08a6cab47e96735 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix comment copy/paste-o.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136281 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 29e85bc7285337973924501cad7e7effafd91e65 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQASX and UQSAX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136280 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 24a541b79fb9694b6edf19ee288b7c9063653512 |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UQADD16 and UQADD8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136279 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 49f2ceddd25c75373f8a39fa25e8b9db33bcdacc |
28-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for UMULL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136277 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 71725a099e6d0cba24a63f9c9063f6efee3bf76e |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for UMLAL.
Fix parsing of the 's' suffix for the mnemonic. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136274 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 2adba4156b83bd005bb704908bb36697e1ecabda |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UMAAL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136272 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| f36b0a2ee4fe1e67778b60daf6020574e62ca672 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UHSUB16 and UHSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136267 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 66c898224456990e511b71e498046736c0478079 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UHADD16, UHADD8 and UHASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136266 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| fb8989e64024547e4ad5ab6fe4d94fe146a7899f |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding of SBFX and UBFX.
Encode the width operand as it encodes in the instruction, which simplifies
the disassembler and the encoder, by using the imm1_32 operand def. Add a
diagnostic for the context-sensitive constraint that the width must be in
the range [1,32-lsb].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136264 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| b6854ad2b1aad78660e7a3421d9c0dbdeaa3c975 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for UADD16, UADD8 and UASX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136261 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 8b3fd56e0f61038ea45b0d1eaff57196d80579aa |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for TST instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136260 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| f1ae78af1796ec122e3cf75ab4826495eb5a4e8d |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for TEQ instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136259 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 06470311c574da4f83f91400234a1e1fc4c9ea1b |
27-Jul-2011 |
Owen Anderson <resistor@mac.com> |
Refactor the STRT and STRBT instructions to distinguish between the register-addend and immediate-addend versions. Temporarily XFAIL the asm parsing tests for these instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136255 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode2.s
|
| 7e1547ebf726a40e7ed3dbe89a77e1b946a8e2d0 |
27-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests
for the sign extend instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136252 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 189610f9466686a91fb7d847b572e1645c785323 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM diagnostics for ldrexd/stredx out of order paired register operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136110 91177308-0d34-0410-b5e6-96231b3b80d8
iagnostics.s
|
| 36711e4a3c0b53000ea594233bd619dbf252558c |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for load/store exclusive instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136105 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 4f6f13db1a8a491ecab6af64549fbdc23cb5ba56 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SWP[B] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136098 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| ed8384806e56952c44f8a717c1ef54a8468d2c8d |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding for SVC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136090 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 873db3eebae3cf1e0931149896f262d17a4dc79d |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SUB instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136089 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| a46c658c6619e979a54ec1e4dc919b3a0319129a |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM STM tests. Fix check: prefix for diagnostic tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136088 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 185f92e7d019bc52413a2b082d61e35c80f8b597 |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAX, SSUB16 and SSUB8.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136013 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| f49433523e8a39db6d83503e312ae55160eed90a |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT16 instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136006 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 580f4a9c1c2fcbb8877463f873c6e9ca2a5ccf9f |
26-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SSAT instruction.
Fix the Rn register encoding for both SSAT and USAT. Update the parsing of the
shift operand to correctly handle the allowed shift types and immediate ranges
and issue meaningful diagnostics when an illegal value or shift type is
specified. Add aliases to parse an ommitted shift operand (default value of
'lsl #0').
Add tests for diagnostics and proper encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135990 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 6ab4e3dd2375c3dcee06dde37437dc0c5a99aa24 |
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add FIXME
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135819 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 0e76edf8c05c5107acb687b898fea686ae756c38 |
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing tests for SMULWB, SMULWT, SMUSD and SMUSDX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135818 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| bf2845c0d8a77d24e9971871badeba8cee7b2648 |
23-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding updates.
Tests for SMULBB, SMLALBT, SMLALTB, SMLALTT, and SMULL. Fix parsing of SMULLS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135817 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 6808f21757f4f2be05a3b12a67d9360b4f9f62e2 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests.
Add tests for SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR,
SMMUL, SMMULR, SMUAD and SMUADX.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135810 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 44a456332f1f41d1e0b2815d93e47a88d501ee6e |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SMLAWB/SMLAWT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135800 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| ce501030d9b0213d951fbf05f928ac75b06b5a3a |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests.
Tests for SMLAL, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLALD, and SMLALDX
instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135798 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| b544f68b70475f06a8ec39c874297549edc0f695 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding of SMLAL instruction.
Fix parsing of carry-setting variant SMLALS and add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135797 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| b206daaec1a2ec25e99fbdc413cd0866cec160b2 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing of SMLAD{X} instructions.
Fix encoding of destination register. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135796 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 0ffd4a09dfb1ee56ec335fed0d15954f92cfa5b3 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for assembly parsing and encoding SMLA* instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135795 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 7c9fbc0340aff9e20fd9009be23ffd279c1c0a7d |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SMC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 248e6c328c06afc2a6af6b95a1a8a41c1b53055c |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM encoding and assembly parsing tests.
Add tests for SHADD8, SHADD16, SHASX, SHSUB8, and SHSUB16.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135780 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| c27d4f9ea0cb9064d3e2cadb384d73e95e9de449 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding for SETEND instruction.
Add parsing and diagnostics for malformed inputs. Tests for diagnostics and
for correct encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135776 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 9076b6e8f43c7eade7e0b667081f94df097e85c3 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing and encoding tests for SEL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135772 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 8409f047312da0318af2a2fce162810ca3a95da3 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for SBC instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135718 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 8ae45af7941dc3e78859ba3624676081590c435d |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for SADD/SASX parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135715 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| f790193aec11747bb35206d2c79e0c5ffbc6dc7f |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSC instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135713 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 86fdff0fa79b2c00cb68a2961cca0466eb50d666 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing support for RSB instruction.
Add two-operand instruction aliases. Add parsing and encoding tests for
variants of the instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135712 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 616fbdf987170addd0d8f75f4fd677589d54cd75 |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for RBIT, REV, REV16 and REVSH.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135710 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| a4c34ab54485f64d3b962a499526825a7a0d4bbc |
22-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encodings tests for saturating arithmetic insns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135709 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 10c7d70a4e843b3006db9f5f583d6f6f56cc245e |
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing POP/PUSH mnemonics.
Aliases for LDM/STM. The single-register versions should encode to LDR/STR
with writeback, but we don't (yet) get that correct. Neither does Darwin's
system assembler, though, so that's not a deal-breaker of a limitation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135702 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 61b1b21e9ad2b8af163a352766eeb159979f4ff2 |
21-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM PKH assembly parsing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135696 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 88d1bc832ca5b458c8460929227be8eae6c6bdc3 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add parsing/encoding tests for ARM ORR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135602 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| a67851445902d1fc01fa2a37a3dfc347af949f84 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Consolidate ARM NOP encoding test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135600 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| c3635c2e928a7ecde11398ff272411f6dea2dcd2 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for MVN
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135599 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| ab40f4b737b0a87c4048a9ad2f0c02be735e3770 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MUL instruction.
Correctly handle 's' bit and predication suffices. Add parsing and encoding
tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135596 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| b29b4dd988c50d5c4a15cd196e7910bf46f30b83 |
20-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Tweak ARM assembly parsing and printing of MSR instruction.
The system register spec should be case insensitive. The preferred form for
output with mask values of 4, 8, and 12 references APSR rather than CPSR.
Update and tidy up tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 80d01dd3d19a84621324ac444c6749602df7a513 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing of MRS instruction.
Teach the parser to recognize the APSR and SPSR system register names. Add
and update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135527 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| ccfd9313d11aa29551f93fe99428946837c97729 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MRC/MRC2/MRRC/MRRC2.
Add range checking to the immediate operands. Update tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135521 91177308-0d34-0410-b5e6-96231b3b80d8
iagnostics.s
|
| 2317fe1584e02582c616c1c4d15954999ff5525a |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Move mr[r]c[2] ARM tests and tidy up a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135517 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 1a2be4db5b12cb7bfa351bcebd5e94b0decb021f |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM testcases for MOVT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135516 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 5f16057d1e4b711d492091bc555693a03d4a1b6e |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (register).
Correct the handling of the 's' suffix when parsing ARM mode. It's only a
truly separate opcode in Thumb. Add test cases to make sure we handle
the s and condition suffices correctly, including diagnostics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135513 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| ffa3225e26cc1977d20f0d9649fcd6f38a3c4815 |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembly parsing for MOV (immediate).
Add range checking for the immediate operand and handle the "mov" mnemonic
choosing between encodings based on the value of the immediate. Add tests
for fixups, encoding choice and values, and diagnostic for out of range values.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135500 91177308-0d34-0410-b5e6-96231b3b80d8
rm_fixups.s
asic-arm-instructions.s
iagnostics.s
|
| 0ec2aa21d0286339961a5c331ca289751ab1396c |
19-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135499 91177308-0d34-0410-b5e6-96231b3b80d8
rm_fixups.s
|
| 33c16a27370939de39679245c3dff72383c210bd |
15-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM diagnostic when 's' suffix on mnemonic that can't set flags.
For example, "mlss r0, r1, r2, r3".
The MLS instruction does not have a flag-setting variant.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135203 91177308-0d34-0410-b5e6-96231b3b80d8
iagnostics.s
|
| 70d8fcfaa04eb20541b006a8fb97cbc1d3033cc4 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some testcases for ARM MLA/MLS instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135196 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| c8ae39e746a20dc326def0ccfc052df3e21f16d3 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCRR/MCRR2 immediate operand range checking.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135192 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
iagnostics.s
|
| e540c7422ca13c950f0e8f6f93af7225bb7742a9 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM MCR/MCR2 assembly parsing operand constraints.
The immediate operands are restricted to 0-7. Enforce that when parsing
assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135189 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
iagnostics.s
|
| 1134be2428f0f26314ae25020f0081b860a0084d |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Enable some tests we now handle correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135185 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 3b14a5c5469176effb921d91d4494f0aa2919fd0 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Update ARM Assembly of LDM/STM.
ldm/stm are the cannonical spellings for ldmia/stmia, so use them as such.
Update the parsing/encoding tests accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135168 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 791feea10071223886e2fe2bfa0e1f4cb2c0ce74 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM ISB assembly parsing tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135158 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 9dec507ecb212a7c94659e9b5a9da66cb4b39ea3 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM ISB instruction assembly parsing.
The ISB instruction takes an optional operand, just like DMB/DSB. Typically
only 'sy' is meaningful.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135156 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 00a66653cbe56dfbdb831172b54097bf8256a191 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM tests for EOR instruction parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135119 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 6a86feafa8c26ffd4b9edb3a3eab946724842051 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Remove duplicate tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135117 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| e77494e3e3da59afaa51d1bbcf732fa2851d865d |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DSB instruction.
Add instalias for default 'sy' option. Add tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135116 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 032434d622b6cd030a60bb9045a520c93b0d7d68 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DMB instruction.
Flesh out the options supported for the instruction. Shuffle tests a bit and
add entries for the rest of the options. Add an alias to handle the default
operand of "sy".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135109 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 6f9f8845028d4d3b96c33417398034a71137d867 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135102 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 14ab1c3387a240a914cf8b1907bb3609bae72269 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM parsing and encoding tests for CMN/CMP.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135098 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| d986bc66bc56251c2b7d5b9a89df14c4760568fc |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Shuffle ARM assembly tests a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135095 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
asic-arm-instructions.s
|
| 83ab070fc1fbb02ca77b0a37e6ae0eacf58001e1 |
14-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for CDP[2] immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135092 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 9bb098ad3a3c93aec50a4a63e6894472727f8d88 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135081 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
humb2.s
|
| f333d471d2cdd47d830dfe3a3e40efbb106c100d |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcases for ARM assembly BX/BXJ instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135078 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 37023b05c84000373fcfc0871edad3c2b995be33 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Testcases for ARM assembly BLX/BL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135072 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| fff76ee7ef007b2bb74804f165fee475e30ead0d |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Range checking for 16-bit immediates in ARM assembly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135071 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
iagnostics.s
|
| 21101d60ce94f51651f71eeb61ceb8264eccac83 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'BKPT' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135063 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 76cbe02cdd57a297d9c6f1e5106e4718abd7ff9f |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix copy-pasto.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135062 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| e52240c3705f3133eb8c4ebb4220054c68de2651 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'BIC' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135061 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 7ed6d22e9637c52b3511ac6907830251d1124e60 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add some FIXMEs.
Keeping the instructions in alphabetical order, just like in the ARM ARM.
Adding FIXMEs for skipped instructions when adding tests out of order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135060 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 59642c260064a0c9140e048d702a21830020487f |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'AND' instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135056 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 19906729a490744ce3071d20e3d514cadc12e6c5 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.
Add some tests for the diagnostics we do want.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135055 91177308-0d34-0410-b5e6-96231b3b80d8
iagnostics.s
|
| da9f278c741e8ced7c1652720270918eb04ed348 |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add tests for ARM parsing of 'ADD' instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135053 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 37ee464ea98544d3ed84cec6dde5f769ce003d5f |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Destination register operand is optional for ADC and SBC ARM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135052 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| e8606dc7c878d4562da5e3e5609b9d7d734d498c |
13-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135049 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| dc89561fecf100d6c32d73c7b009fd73e51be688 |
12-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Add check for predicate w/o S bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134987 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 3f00e317064560ad11168d22030416d853829f6e |
11-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134903 91177308-0d34-0410-b5e6-96231b3b80d8
asic-arm-instructions.s
|
| 589130fac11bc8c186736161600575c3ed6acc5b |
11-Jul-2011 |
Jim Grosbach <grosbach@apple.com> |
Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
displayed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134902 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 59ee62d2418df8db499eca1ae17f5900dc2dcbba |
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
ode-switch.s
|
| 32869205052430f45d598fba25ab878d8b29da2d |
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add support for ARM / Thumb mode switching with .code 16 and .code 32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134760 91177308-0d34-0410-b5e6-96231b3b80d8
ode-switch.s
|
| 39dfb0ff848be6b380ca81ff95d4ca4e0ae09c76 |
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134590 91177308-0d34-0410-b5e6-96231b3b80d8
refetch.ll
|
| adf7366771ebc78b3eee3c86b95e255ff5726da7 |
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Thumb2 asm syntax optional destination operand for binary operators.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
and r1, #ff
and r1, r1, #ff
rdar://9672867
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133973 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 6b8f1e35eacba34a11e2a7d5f614efc47b43d2e3 |
28-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembly support for Thumb mov-immediate.
Correctly parse the forms of the Thumb mov-immediate instruction:
1. 8-bit immediate 0-255.
2. 12-bit shifted-immediate.
The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic,
but is not yet supported. More parser logic necessary there due to fixups.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133966 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| fbd01783a67dd2bedd8197308ef00d4ad767fcd3 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for ldmfd/stmfd mnemonics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133936 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 0d06bb954881dc7ff0e2333d5a3e249b7bb304d0 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM assembler support for vpush/vpop.
Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple
writeback instructions w/ SP as the base pointer.
rdar://9683231
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133932 91177308-0d34-0410-b5e6-96231b3b80d8
push-vpop.s
|
| 0ff9220ccb6ef419ba4d3a4daf98f4658a9e5134 |
27-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
ARM Assembly syntax support for arithmetic implied dest operand.
When the destination operand is the same as the first source register
operand for arithmetic instructions, the destination operand may be omitted.
For example, the following two instructions are equivalent:
sub r2, r2, #6
sub r2, #6
rdar://9682597
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133925 91177308-0d34-0410-b5e6-96231b3b80d8
rm-arithmetic-aliases.s
|
| 75c2b2028bd898cb8448fcf0fa76c3d47843a164 |
25-Jun-2011 |
Jim Grosbach <grosbach@apple.com> |
Move ARM-specific test to ARM directory.
Hopefully make the x86-target-only Windows bots happy.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133856 91177308-0d34-0410-b5e6-96231b3b80d8
humb2-movt-fixup.s
|
| 895c1e2deea3e6118b159c26b3f86d40a37e8501 |
31-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value
must be encoded decremented by one. Only add encoding tests for ssat16
because ssat can't be parsed yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132324 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| 06a8d5496788ac74a69dc68680bad48ca1814b43 |
28-May-2011 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move ARM specific test into the ARM subdir.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132255 91177308-0d34-0410-b5e6-96231b3b80d8
lf-thumbfunc.s
|
| be64b394317feb8d7bcb732bdfb35e0b286efd4c |
28-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132233 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| 56926a39619bd644c83c4128f0b55189e52707d7 |
25-May-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix PR9762
Enable the parsing of the operand "cpsr_all" for the ARM msr instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132026 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| b8adb8af0fa9d1405fcf2edb95f4b1b8d1904716 |
20-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
adds some attributes to attribute section when cpu is "xscale"
(this is what used in Android NDK, when architecture is ARMv5)
patch by Koan-Sin Tan
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131751 91177308-0d34-0410-b5e6-96231b3b80d8
scale-attributes.ll
|
| 298c8e12ea063f7522c59d2a297b47a879b6ed55 |
20-May-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
fixes target address tBL and tBLX and sets relocation type
of tBL/tBLX to R_ARM_THM_CALL (ARM ELF 4.7.1.6)
Patch by koan-sin tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131748 91177308-0d34-0410-b5e6-96231b3b80d8
lf-thumbfunc-reloc.ll
|
| 861b9c6a397f2ed4b5601cacbc9121d0b07d1f65 |
19-May-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
This fixes one divergence between LLVM and binutils for ARM in the
text section.
Assume the following bit of annotated assembly:
.section .data.rel.ro,"aw",%progbits
.align 2
.LAlpha:
.long startval(GOTOFF)
.text
.align 2
.type main,%function
.align 4
main: ;;; assume "main" starts at offset 0x20
0x0 push {r11, lr}
0x4 movw r0, :lower16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-4) + 8) = -20
0x8 movt r0, :upper16:(.LAlpha-(.LBeta+8))
;;; ==> (.AddrOf(.LAlpha) - ((.AddrOf(.LBeta) - .AddrOf(".")) + 8)
;;; ==> (??? - ((16-8) + 8) = -16
0xc ... blah
.LBeta:
0x10 add r0, pc, r0
0x14 ... blah
.LGamma:
0x18 add r1, pc, r1
Above snippet results in the following relocs in the .o file for the
first pair of movw/movt instructions
00000024 R_ARM_MOVW_PREL_NC .LAlpha
00000028 R_ARM_MOVT_PREL .LAlpha
And the encoded instructions in the .o file for main: must be
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec i.e. -20
28: e34f0ff0 movt r0, #65520 ; 0xfff0 i.e. -16
However, llc (prior to this commit) generates the following sequence
00000020 <main>:
20: e92d4800 push {fp, lr}
24: e30f0fec movw r0, #65516 ; 0xffec - i.e. -20
28: e34f0fff movt r0, #65535 ; 0xffff - i.e. -1
What has to happen in the ArmAsmBackend is that if the relocation is PC
relative, the 16 bits encoded as part of movw and movt must be both addends,
not addresses. It makes sense to encode addresses by right shifting the value
by 16, but the result is incorrect for PIC.
i.e., the right shift by 16 for movt is ONLY valid for the NON-PCRel case.
This change agrees with what GNU as does, and makes the PIC code run.
MC/ARM/elf-movt.s covers this case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131674 91177308-0d34-0410-b5e6-96231b3b80d8
lf-movt.s
|
| 18901d63bf0deb117bd7a1ad69b25faa422ce378 |
11-May-2011 |
Owen Anderson <resistor@mac.com> |
Fix encoding of Thumb BLX register instructions. Patch by Koan-Sin Tan.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131189 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| f695b3ad628625a1b1250c65716df1ee96b3d975 |
04-May-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Explicitly request -join-physregs for some tests that depend on it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130855 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 12bb2958c4f335e79c831136d2dfed9f375f06ff |
05-Apr-2011 |
Johnny Chen <johnny.chen@apple.com> |
Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
<byte> is the numeric value of abcdefgh, in the range 0-255
<rot> is twice the numeric value of rotation, an even number in the range 0-30.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128897 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| ac79e4c82f201c30a06c2cd05baebd20f5b49888 |
04-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
index mode to print.
- Testcases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128832 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode3.s
|
| ae0855401b8c80f96904b6808b0bc4c89216aecd |
01-Apr-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Apply again changes to support ARM memory asm parsing. I removed
all LDR/STR changes and left them to a future patch. Passing all
checks now.
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
fix the encoding wherever is possible.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128689 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode2.s
|
| 48a36158ec09f3f47e9e84af7feb6fcf9fccfd28 |
31-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Remove stray empty test file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128640 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode2.s
|
| b41aaab5a1769f4df04d566da37866ac91b6ee9e |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Revert r128632 again, until I figure out what break the tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128635 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode2.s
|
| bcd3a9cd84d3bb143075d31bdf631f621f44f9e7 |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Reapply r128585 without generating a lib depedency cycle. An updated log:
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_{PRE,POST} fixing the encoding wherever is possible.
- Move all instructions which use am2offset without a pattern to use
addrmode2.
- Add a new encoding bit to describe the index mode used and teach
printAddrMode2Operand to check by the addressing mode which index
mode to print.
- Testcases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128632 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode2.s
|
| e4345c9977e65b14fa4b93d19c7e67a7b15f7f40 |
31-Mar-2011 |
Matt Beaumont-Gay <matthewbg@google.com> |
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and"
This revision introduced a dependency cycle, as nlewycky mentioned by email.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode2.s
|
| 40829ed6f5e449fa33a9cd7022ce6c3941dace3d |
31-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and
{STR,LDC}{2}_PRE.
- Fixed the encoding in some places.
- Some of those instructions were using am2offset and now use addrmode2.
Codegen isn't affected, instructions which use SelectAddrMode2Offset were not
touched.
- Teach printAddrMode2Operand to check by the addressing mode which index
mode to print.
- This is a work in progress, more work to come. The idea is to change places
which use am2offset to use addrmode2 instead, as to unify assembly parser.
- Add testcases for assembly parser
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128585 91177308-0d34-0410-b5e6-96231b3b80d8
rm_addrmode2.s
|
| 505f3cd2965e65b6b7ad023eaba0e3dc89b67409 |
24-Mar-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add asm parsing support w/ testcases for strex/ldrex family of instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128236 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| 7c18fa87a4d4ed8b0cfe1ec65597c748c6d91ca9 |
20-Mar-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Write the section table and the section data in the same order that
gun as does. This makes it a lot easier to compare the output of both
as the addresses are now a lot closer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127972 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-01.ll
lf-reloc-02.ll
lf-reloc-03.ll
|
| 0082830cb26248178fe5cc9bbdbd00881556c33d |
18-Mar-2011 |
Owen Anderson <resistor@mac.com> |
Add support to the ARM asm parser for the register-shifted-register forms of basic instructions like ADD. More work left to be done to support other instances of shifter ops in the ISA.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127917 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 899eaa35696bb0a9a625acd70a14876834af6cc5 |
11-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Roll r127459 back in:
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127498 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 950d3db5f478a84242a90cafce0d8dfc4f8b1152 |
11-Mar-2011 |
Daniel Dunbar <daniel@zuster.org> |
Revert r127459, "Optimize trivial branches in CodeGenPrepare, which often get
created from the", it broke some GCC test suite tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127477 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 592ca3fda918c2066d9d78ed360e5fd69066fda7 |
11-Mar-2011 |
Cameron Zwarich <zwarich@apple.com> |
Optimize trivial branches in CodeGenPrepare, which often get created from the
lowering of objectsize intrinsics. Unfortunately, a number of tests were relying
on llc not optimizing trivial branches, so I had to add an option to allow them
to continue to test what they originally tested.
This fixes <rdar://problem/8785296> and <rdar://problem/9112893>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127459 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 620d0cc7ac8319fe66168288f8ca0509f87c46c1 |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
* Correct encoding for VSRI.
* Add tests for VSRI and VSLI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127297 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| c04a9dea7873bcf2a1e68b9eba9b5854021e989a |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Correct the encoding for VRSRA and VSRA instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127294 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 7c6b608a7cb33e628e3906a8395a7ba47a6b966b |
09-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
* Fix VRSHR and VSHR to have the correct encoding for the immediate.
* Update the NEON shift instruction test to expect what 'as' produces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127293 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 591432136c78ab61ac1233cb813077e4c7c2f25e |
08-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
A few more tests for instruction encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127209 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 3116dce33840a115130c5f8ffcb9679d023496d6 |
08-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.
No functionality change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127193 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| a656b63ee4d5b0e3f4d26a55dd4cc69795746684 |
01-Mar-2011 |
Bill Wendling <isanbard@gmail.com> |
Narrow right shifts need to encode their immediates differently from a normal
shift.
16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126723 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.s
|
| 98ea4ce516f40beb3efe63e8fb9eee7a3124a7d9 |
25-Feb-2011 |
Chris Lattner <sabre@nondot.org> |
split this test into arch specific pieces, so the ARM
test isn't run when the arm backend isn't built. This
fixes PR9327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126500 91177308-0d34-0410-b5e6-96231b3b80d8
racket-exprs.s
|
| 93c65e6e661eda75711363bdd5ca15909920e1f0 |
24-Feb-2011 |
Joerg Sonnenberger <joerg@bec.de> |
Restore r125595 (reverted in r126336) with modifications:
Introduce a variable in the AsmParserExtension whether [] is valid in an
expression. If it is true, parse them like (). Enable this for ELF only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126443 91177308-0d34-0410-b5e6-96231b3b80d8
racket-darwin.s
|
| 3fe3424a2149a67f7468fc7a441d6cb6bb79ca33 |
24-Feb-2011 |
Devang Patel <dpatel@apple.com> |
Move arch specific tests in arch specific directories.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126401 91177308-0d34-0410-b5e6-96231b3b80d8
arwin-ARM-reloc.s
arwin-Thumb-reloc.s
ull_line_comment.s
|
| 584bf7bb03e4cf1475b26851edcc1ddb66b85028 |
18-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add assembly parsing support for "msr" and also fix its encoding. Also add
testcases for the disassembler to make sure it still works for "msr".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125948 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| a2b6e4151b75248f9dbf8067186cba673520f8f4 |
14-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix encoding and add parsing support for the arm/thumb CPS instruction:
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125489 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb.s
humb2.s
|
| b9db0c50d84b06b4b567c29375b7db92b5dab077 |
10-Feb-2011 |
Jim Grosbach <grosbach@apple.com> |
Do AsmMatcher operand classification per-opcode.
When matching operands for a candidate opcode match in the auto-generated
AsmMatcher, check each operand against the expected operand match class.
Previously, operands were classified independently of the opcode being
handled, which led to difficulties when operand match classes were
more complicated than simple subclass relationships.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125245 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 706d946cfe44fa93f482c3a56ed42d52ca81b257 |
07-Feb-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing dmb/dsb instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125055 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| 953a2a3dee46bebd70b129fd62709710f5f2b033 |
07-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Teach ARM/MC/ELF about gcc compatible reloc output to get past odd linkage
failures with relocations.
The code committed is a first cut at compatibility for emitted relocations in
ELF .o.
Why do this? because existing ARM tools like emitting relocs symbols as
explicit relocations, not as section-offset relocs.
Result is that with these changes,
1) relocs are now substantially identical what to gcc outputs.
2) larger apps (including many spec2k tests) compile, cross-link, and pass
Added reminder fixme to tests for future conversion to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124996 91177308-0d34-0410-b5e6-96231b3b80d8
lf-reloc-01.ll
lf-reloc-02.ll
lf-reloc-03.ll
|
| 2d7a53aec2c6426eba9e5dd6462cc9e86432b410 |
04-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Teach ARM/MC/ELF about EF_ARM_EABI_VERSION. The magic number is set to
5 to match the current doc.
Added FIXME reminder Make it really configurable later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124899 91177308-0d34-0410-b5e6-96231b3b80d8
lf-eflags-eabi.s
|
| 685c350ae76b588e1f00c01a511fe8bd57f18394 |
04-Feb-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
(yes, this is different from R_ARM_CALL)
- Adds a new method getARMBranchTargetOpValue() which handles the
necessary distinction between the conditional and unconditional br/bl
needed for ARM/ELF
At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...
Added a few FIXME's for future naming fixups in ARMInstrInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124895 91177308-0d34-0410-b5e6-96231b3b80d8
rm_fixups.s
|
| 4d98ee52348c23a7a2f59a4235941fcbb668a2b9 |
01-Feb-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix test for non-darwin targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124640 91177308-0d34-0410-b5e6-96231b3b80d8
refetch.ll
|
| c3a20bab7571ff95525252c379198e67b65d0f1d |
28-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix PLD encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124458 91177308-0d34-0410-b5e6-96231b3b80d8
refetch.ll
|
| 106df6da366c0abc6a3937767fe008d02cacef4c |
26-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add encoding testcases for ARM vcvtr variations
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124289 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 1b10d5be40313b4e246e85cf375dfa3452ab306b |
26-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124288 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb.s
humb2.s
|
| 030160073d8ec7d5fc1d928d9c8b6173d3a5e0cc |
21-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm",
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123975 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| 1115c472038b19dfcc3ff44b8bf6711ebcfc3dc4 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add testcases for clz encoding
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123937 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| e47f3751d7770916f250a00a84316d412e959c00 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding and parsing of clrex instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123936 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| 8dd37f7b7dca7907f9f070dc96359f242e102163 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add cdp/cdp2 instructions for thumb/thumb2
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123929 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
humb2.s
|
| b32f7a5f4bc678c052db40cbb4ac8617c134aa24 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
- Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123927 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 6b3a999f227139a3be7df6b5aea7a7d01ce94851 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr*2 and mr*c2 support to thumb2 targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123919 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| fa5bd27fbe5188ca708ac0dda4f32d90505da9f5 |
20-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add mcr* and mr*c support to thumb targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| 3abd75bf1dc96ee0cd7e8c1b8331e27672437b8b |
19-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of mrrc and mcrr family of instructions. Also add testcases for mcr and mrc
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123837 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 6cd0b17ba7f7efae41966c4a36ee725523d38575 |
19-Jan-2011 |
Owen Anderson <resistor@mac.com> |
When matching asm operands, always try to match the most restricted type first.
Unfortunately, while this is the "right" thing to do, it breaks some ARM
asm parsing tests because MemMode5 and ThumbMemModeReg are ambiguous. This
is tricky to resolve since neither is a subset of the other.
XFAIL the test for now. The old way was broken in other ways, just ways
we didn't happen to be testing, and our ARM asm parsing is going to require
significant revisiting at a later point anyways.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123786 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 61505907f54d4e7df2f9d90b1ed3a4caa0469d26 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Create two new generic classes to represent the following VMRS/VMSR variations:
vmrs reg, fpexc
vmrs reg, fpsid
vmsr fpexc, reg
vmsr fpsid, reg
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
humb2.s
|
| e7255a80e308c7f67d25b0b247ed791a99ea3a4e |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix MRS encoding for arm and thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123778 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| 892fc6d7b64364b230261daa967518a71748c01b |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Fix the encoding of t2ISB by using the right class and also parse it correctly
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123776 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| fdcee77887372dbf6589d47cc33094965b679f24 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Follow the current hack set and enable the correct parsing of bkpt while in thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123772 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb.s
|
| a461d4222877f43588da38c466145f38dd74e229 |
18-Jan-2011 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add support for parsing and encoding ARM's official syntax for the BFI instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123770 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
humb2.s
|
| 2e3cea3153ab957af01925580d912be060cb00cf |
18-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Start marking T2 address operands as such, for the benefit of the parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123722 91177308-0d34-0410-b5e6-96231b3b80d8
humb2_instructions.s
|
| f3eb3bba1614a7935b44fc963a805088d71267f3 |
14-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Completed :lower16: / :upper16: support for movw / movt pairs on Darwin.
- Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first.
- Added support for Thumb2 :lower16: and :upper16: fix up.
- Added :upper16: and :lower16: relocation support to mach-o object writer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123424 91177308-0d34-0410-b5e6-96231b3b80d8
lf-movt.s
ilo-16bit-relocations.s
|
| 7597212abced110723f2fee985a7d60557c092ec |
13-Jan-2011 |
Evan Cheng <evan.cheng@apple.com> |
Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step
in the right direction. It eliminated some hacks and will unblock codegen
work. But it's far from being done. It doesn't reject illegal expressions,
e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123369 91177308-0d34-0410-b5e6-96231b3b80d8
lf-movt.s
ilo-16bit-relocations.s
|
| 7caebff83d90a59aa74876ff887e822387f479e0 |
12-Jan-2011 |
Bill Wendling <isanbard@gmail.com> |
Sort the register list based on the *actual* register numbers rather than the
enum values we give to them. <rdar://problem/8823730>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123321 91177308-0d34-0410-b5e6-96231b3b80d8
eg-list.s
|
| 86a97f2e4d0cde5e992f52ac287da0de687e0110 |
12-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
1. Support ELF pcrel relocations for movw/movt:
R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC.
2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum.
3. Add support for 3 new elf section types (no-ops)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123294 91177308-0d34-0410-b5e6-96231b3b80d8
lf-movt.s
|
| 9081b4b4cf89a161246e037f4817c69de2fcdf82 |
12-Jan-2011 |
Jason W Kim <jason.w.kim.2009@gmail.com> |
Workaround for bug 8721.
.s Test added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123292 91177308-0d34-0410-b5e6-96231b3b80d8
lf-movt.s
|
| 352e148cbe6498a6dd31b7fc71df7cd23c4b4d10 |
11-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the
carry setting flag from the mnemonic.
Note that this currently involves me disabling a number of working cases in
arm_instructions.s, this is a hopefully short term evil which will be rapidly
fixed (and greatly surpassed), assuming my current approach flies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123238 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 8ab1112bdc30b8675bb12431d8b5b270da42f1b5 |
10-Jan-2011 |
Daniel Dunbar <daniel@zuster.org> |
McARM: Flush out hard coded known non-predicated mnemonic list.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123189 91177308-0d34-0410-b5e6-96231b3b80d8
eon-absdiff-encoding.s
eon-bitcount-encoding.s
eon-pairwise-encoding.s
|
| 0406356cd4cb7b689e2472faa8dfb7d721f9d274 |
15-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Add Neon VCVT instructions for f32 <-> f16 conversions.
Clang is now providing intrinsics for these and so we need to support them
in the backend. Radar 8068427.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121902 91177308-0d34-0410-b5e6-96231b3b80d8
eon-convert-encoding.s
eont2-convert-encoding.s
|
| 8d1b7e57e56015576fd489a57d74c53b98c5a56f |
15-Dec-2010 |
Bob Wilson <bob.wilson@apple.com> |
Fix misspelled target triples in MC/ARM test commands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121901 91177308-0d34-0410-b5e6-96231b3b80d8
eon-abs-encoding.s
eon-absdiff-encoding.s
eon-bitcount-encoding.s
eon-bitwise-encoding.s
eon-cmp-encoding.s
eon-convert-encoding.s
eon-dup-encoding.s
eon-minmax-encoding.s
eon-mov-encoding.s
eon-mul-accum-encoding.s
eon-mul-encoding.s
eon-neg-encoding.s
eon-pairwise-encoding.s
eon-reciprocal-encoding.s
eon-reverse-encoding.s
eon-satshift-encoding.s
eon-shift-encoding.s
eon-shiftaccum-encoding.s
eon-shuffle-encoding.s
eon-sub-encoding.s
eon-table-encoding.s
eont2-abs-encoding.s
eont2-absdiff-encoding.s
eont2-bitcount-encoding.s
eont2-bitwise-encoding.s
eont2-cmp-encoding.s
eont2-convert-encoding.s
eont2-dup-encoding.s
eont2-minmax-encoding.s
eont2-mov-encoding.s
eont2-mul-accum-encoding.s
eont2-mul-encoding.s
eont2-neg-encoding.s
eont2-pairwise-encoding.s
eont2-reciprocal-encoding.s
eont2-reverse-encoding.s
eont2-satshift-encoding.s
eont2-shift-encoding.s
eont2-shiftaccum-encoding.s
eont2-shuffle-encoding.s
eont2-sub-encoding.s
eont2-table-encoding.s
|
| 53ef11884ff273715f1924ea13853ec18510dae1 |
15-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Add some more MC tests for ARM arithmetic instructions that update or don't
update the condition codes. These come from my test generator and are just
the ones that MC currently assembles correctly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121830 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| abfbac52df836460392186a61619fe266b40fa8c |
14-Dec-2010 |
Daniel Dunbar <daniel@zuster.org> |
MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121772 91177308-0d34-0410-b5e6-96231b3b80d8
rm_fixups.s
|
| 193c3acbe5cdb60767d114016970e898c7502d7a |
09-Dec-2010 |
Kevin Enderby <enderby@apple.com> |
Add support for parsing ARM arithmetic instructions that update or don't update
the condition codes. Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix. The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present. Four simple test cases added for now, lots more to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121401 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| d91f4e40e6312304c60c83c3dd93f769a39a9772 |
03-Dec-2010 |
Jim Grosbach <grosbach@apple.com> |
Encode the 32-bit wide Thumb (and Thumb2) instructions with the high order
halfword being emitted to the stream first. rdar://8728174
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120848 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-abs-encoding.s
eont2-add-encoding.s
eont2-cmp-encoding.s
eont2-convert-encoding.s
eont2-minmax-encoding.s
eont2-mul-encoding.s
eont2-neg-encoding.s
eont2-reciprocal-encoding.s
eont2-reverse-encoding.s
eont2-satshift-encoding.s
eont2-shift-encoding.s
eont2-shiftaccum-encoding.s
eont2-shuffle-encoding.s
eont2-sub-encoding.s
|
| 7f2abbf268aaa1c010a29649474c8f69e1521e25 |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for more forms of Thumb2 loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120436 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| ef4a68badbde372faac9ca47efb9001def57a43d |
30-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add parsing for the Thumb t_addrmode_s4 addressing mode. This can almost
certainly be made more generic. But it does allow us to parse something like:
ldr r3, [r2, r4]
correctly in Thumb mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120408 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| 6af50f7dd12d82f0a80f3158102180eee4c921aa |
30-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Correct Thumb2 encodings for a much wider range of loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120364 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 75579f739fbc99a92a15f3ce75bbd7628ba00f8c |
29-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for basic loads and stores.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120340 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 2f17bf2a4406d89b5e127306cbd0fc862e0a6bd5 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add more Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120279 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| 5cbbf68e35a053c904548564da13d4a8596f988b |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
More Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120278 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| d19ac0c75a019273e03922e2252ed262578a43d1 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add Thumb encodings for REV instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120277 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| 849f2e381e4e83dc4f60e4a1fe6e6bb47bde8248 |
29-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add more Thumb encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120272 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| af2b573614c7d853879ff24eb9a86d1c36acc198 |
21-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for ARM "trap" instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
imple-encoding.ll
humb.s
|
| 602890dd8ef53c6e8d60a2752b97940f7a58de1a |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add MC encodings for some Thumb instructions. Test for a few of them. The "bx
lr" instruction cannot be tested just yet. It requires matching a "condition
code", but adding one of those makes things go south quickly...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119774 91177308-0d34-0410-b5e6-96231b3b80d8
humb.s
|
| 50d0f5894448aff6eb02ad63da55ecf26b54aeb8 |
19-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for parsing the writeback ("!") token.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119761 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| d2f76ce159cf7b04eb1658bf5d7b0e010909e0e3 |
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119756 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 71c11825bf1673baad44274ff71e8df1be938f5e |
19-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fix encodings for pkhbt, and fix some tests where I accidentally tested ARM mode instead of Thumb2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119755 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 612fb5b9a6472f8e1cea8a4f771238840f4eaa1c |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119737 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 821752e2e601b2e4c0bb83cb341892c853f16d0a |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out the set of Thumb2 multiplication operator encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119733 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 35141a9ba3ce92281cdbe1ccd0f6b5a42398249c |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Try again at providing Thumb2 encodings for basic multiplication operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119601 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 424216453fe2d16379fbb6c3310004b997d3771d |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r119593 while I figure out my testing disagrees with the buildbot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119597 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 18333616cd824bee3abecd607d3aa432b5cf507d |
18-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct Thumb2 encodings for basic multiplication operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119593 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 2f7aed39a3082a3e0bb35475e8ed0cb782fef4b5 |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Second attempt at correct encodings for Thumb2 bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119575 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 5aba9f694fbfb78df2aa2a228e85ba4c27f3037b |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Revert r119551, which broke buildbots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119555 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 23465a06f4f4fa098f99cf91e81ed8f26f962f3f |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for bitfield instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119551 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 46c478e80255bb1475e712ebb119808a9d0b9e12 |
17-Nov-2010 |
Owen Anderson <resistor@mac.com> |
More miscellaneous Thumb2 encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119546 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 0f6307561359fac4425a0b9e512931cf96c1ec5b |
17-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Proper encoding for VLDM and VSTM instructions. The register lists for these
instructions have to distinguish between lists of single- and double-precision
registers in order for the ASM matcher to do a proper job. In all other
respects, a list of single- or double-precision registers are the same as a list
of GPR registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| a295eb34a5c8bffa66ffd46b6f9b8e960930eae3 |
16-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Test encodings for LDM and STM.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119315 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| c56dcbf641f1675579e23064b1c7db1c73ca712b |
16-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for mov and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119295 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 2c4c45deb6a7a8521f6039e3da9688be4cac09d2 |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide Thumb2 encodings for sxtb and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119185 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| bb6315d1e48f24e0eefa98b0f572fda8dbb3251f |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add Thumb2 encodings for comparison and shift operators.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119176 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| a99e778ed894402a4468ad0b695716226471d726 |
15-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for mvn and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119170 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 5de6d841a5116152793dcab35a2e534a6a9aaa7a |
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
First stab at providing correct Thumb2 encodings, start with adc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118924 91177308-0d34-0410-b5e6-96231b3b80d8
humb2.s
|
| 8f143913141991baaa535ca0da7c8a81606d6392 |
12-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Fill out support for Thumb2 encodings of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118854 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-absdiff-encoding.s
eont2-bitcount-encoding.s
eont2-bitwise-encoding.s
eont2-convert-encoding.s
eont2-dup-encoding.s
eont2-mov-encoding.s
eont2-mul-accum-encoding.s
eont2-pairwise-encoding.s
eont2-table-encoding.s
|
| 57dac88f775c1191a98cff89abd1f7ad33df5e29 |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct Thumb2 encodings for NEON vst[1,2,3,4] and vld[1,2,3,4].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118843 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-vld-encoding.s
eont2-vst-encoding.s
|
| 410cb57524e3bfb022df20091ae4a5fa1fa7005d |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Flesh out tests for Thumb2 encodings of NEON instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118837 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-cmp-encoding.s
eont2-minmax-encoding.s
eont2-mul-encoding.s
eont2-neg-encoding.s
eont2-reciprocal-encoding.s
eont2-reverse-encoding.s
eont2-satshift-encoding.s
eont2-shift-encoding.s
eont2-shiftaccum-encoding.s
eont2-shuffle-encoding.s
eont2-sub-encoding.s
|
| c7139a6f0d3acd198ab9eb536ea1ec52e61ff130 |
11-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for Thumb2 encodings of NEON data processing instructions, using the new PostEncoderMethod infrastructure.
More tests to come.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118819 91177308-0d34-0410-b5e6-96231b3b80d8
eont2-abs-encoding.s
eont2-add-encoding.s
|
| c24cb3551ed66830b53362f593269873cb53a0c4 |
09-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for ARM's specialized vector-compare-against-zero instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118453 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.s
|
| 080c09229739ec2b13f7bccc361994a8d26b4ed2 |
05-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add codegen and encoding support for the immediate form of vbic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118291 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| 2f46f1f59c17040f7a2c970342f2f1dcc9b78319 |
04-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSTR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 60f4870c221d0496254c78c6e61bc00e4540fc1b |
04-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert VORRIMM to be produced via early target-specific DAG combining, rather than legalization.
This is both the conceptually correct place for it, as well as allowing it to be more aggressive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118204 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| d966817f3cb87897cbec29c967b974924fe939ba |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add support for code generation of the one register with immediate form of vorr.
We could be more aggressive about making this work for a larger range of constants,
but this seems like a good start.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118201 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.s
|
| 7a25825033a53925f6039b77c4cb0b975026b4e1 |
03-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Unlike a lot of NEON instructions, vext isn't _actually_ parameterized by element size. Instead,
all of the different element sizes are pseudo instructions that map down to vext.8 underneath, with
the immediate shifted left to reflect the increased element size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118183 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.s
|
| 92b5a2eb1646b3c1173a5ff3c0073f24ed5ee6a4 |
03-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
The MC code couldn't handle ARM LDR instructions with negative offsets:
vldr.64 d1, [r0, #-32]
The problem was with how the addressing mode 5 encodes the offsets. This change
makes sure that the way offsets are handled in addressing mode 5 is consistent
throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue"
method into an "Imm12" and "addressing mode 5" version. But not to worry! The
majority of the duplicated code has been unified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 5df0e0a61d6ac0e8dcf1a600bdc28d3e4a8db0ad |
02-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work
with immediates up to 16-bits in size. The same logic is applied to other LDR
encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in
VLDR's case). Removing the "12" allows it to be more generic.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
imple-fp-encoding.s
|
| b20594fce621a0b80132a575113c15ad33afc5e9 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the remaining vst variants that we currently generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118087 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| a1a45fd25471e1121887b45ddc50f611f3c5f0aa |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for basic variants for vst3 and vst4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118082 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| d2f3794e4dba7a397eaae62114fffe46213c7d41 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the basic variants for vst2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118068 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| cfebe3a8b1b5b4654761953a9b695901a1b8eaec |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the basic form of vst1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vst-encoding.s
|
| f0ea0f2b1575868cd238391868d8f51370041303 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for the rest of the vld instructions that we generate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118053 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| cf667be17b479fe276fd606b8fd72ccfa3065bb8 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vld2, vld3, and vld4 basic variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117997 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| d9aa7d30aa277fba319ee4bcdb862cd79f1aabe5 |
02-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for the "multiple single elements" form of vld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
eon-vld-encoding.s
|
| 933b314c761f3338ebc59aa089983681274054bd |
01-Nov-2010 |
Bill Wendling <isanbard@gmail.com> |
Use ARM-style comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.s
|
| 95b9766fea46c78f389793d557158077383b9ff4 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Use ARM-style comment syntax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117941 91177308-0d34-0410-b5e6-96231b3b80d8
eon-abs-encoding.s
eon-absdiff-encoding.s
eon-add-encoding.s
eon-bitcount-encoding.s
eon-bitwise-encoding.s
eon-cmp-encoding.s
eon-convert-encoding.s
eon-dup-encoding.s
eon-minmax-encoding.s
eon-mov-encoding.s
eon-mul-accum-encoding.s
eon-mul-encoding.s
eon-neg-encoding.s
eon-pairwise-encoding.s
eon-reciprocal-encoding.s
eon-reverse-encoding.s
eon-satshift-encoding.s
eon-shift-encoding.s
|
| 4845f990081d466ad193d90d1cd6f1d0eb910309 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117939 91177308-0d34-0410-b5e6-96231b3b80d8
eon-table-encoding.ll
eon-table-encoding.s
|
| 60b75fad7e065254d50894aa13790865e5f2785b |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117938 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.ll
eon-sub-encoding.s
|
| 3b5dfcd8fd9edce8019b6d7541e2a3c5159b2852 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117937 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.ll
eon-shuffle-encoding.s
|
| 2bcb989a0b8ad196473b0560c8e017c2ac387562 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117935 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shiftaccum-encoding.ll
eon-shiftaccum-encoding.s
|
| 833c93c7958dbbd9d648f331091fbfbeabf342e6 |
01-Nov-2010 |
Jim Grosbach <grosbach@apple.com> |
Mark ARM subtarget features that are available for the assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117929 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
rm_word_directive.s
eon-abs-encoding.s
eon-absdiff-encoding.s
eon-add-encoding.s
eon-bitcount-encoding.s
eon-bitwise-encoding.s
eon-cmp-encoding.s
eon-convert-encoding.s
eon-dup-encoding.s
eon-minmax-encoding.s
eon-mov-encoding.s
eon-mul-accum-encoding.s
eon-mul-encoding.s
eon-neg-encoding.s
eon-pairwise-encoding.s
eon-reciprocal-encoding.s
eon-reverse-encoding.s
eon-satshift-encoding.s
eon-shift-encoding.s
imple-fp-encoding.s
|
| b8d14a6611276181f9fd0d9b2a1243150e4a5739 |
01-Nov-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117900 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.ll
eon-shift-encoding.s
|
| 52925b60f1cd4cf810524ca05b00a207a926ab9f |
30-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Some instructions end with an "ls" prefix, but it doesn't indicate that they are
conditional. Check for those instructions explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
imple-fp-encoding.s
|
| 05cee0cdb4121bbb52c1ecc9d9e996dcf268ac65 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117708 91177308-0d34-0410-b5e6-96231b3b80d8
eon-satshift-encoding.ll
eon-satshift-encoding.s
|
| 9ae33fe396e5f7c050a60980e00a99435533c02f |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117704 91177308-0d34-0410-b5e6-96231b3b80d8
eon-reverse-encoding.ll
eon-reverse-encoding.s
|
| 82c85b7490c9f12eccbdf5c69b1116f0eb5af036 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117699 91177308-0d34-0410-b5e6-96231b3b80d8
eon-reciprocal-encoding.ll
eon-reciprocal-encoding.s
|
| fea34d38b41c42bb5a4d1d6ab8f8c2e7635d8738 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117696 91177308-0d34-0410-b5e6-96231b3b80d8
eon-pairwise-encoding.ll
eon-pairwise-encoding.s
|
| 5c4966e1e5285b5971f179f8e7b173281a7d92bc |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117694 91177308-0d34-0410-b5e6-96231b3b80d8
eon-neg-encoding.ll
eon-neg-encoding.s
|
| ffe2a4a77d463ea1921c8d7e521fa74ad6cea776 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117693 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.ll
eon-mul-encoding.s
|
| 9fcafb0269f22a362b4a2637ae78e74a3765c23d |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117690 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.ll
eon-mul-accum-encoding.s
|
| 2457b550036862461706511b9c13e000ce95f121 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117689 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.ll
eon-mov-encoding.s
|
| cd410ac70cb1d8041946291d4bc7bfb9366b7d2c |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117686 91177308-0d34-0410-b5e6-96231b3b80d8
eon-minmax-encoding.ll
eon-minmax-encoding.s
|
| 95d3711a159b1db06d4233e8670dcc92ac1e3b70 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117685 91177308-0d34-0410-b5e6-96231b3b80d8
eon-dup-encoding.ll
eon-dup-encoding.s
|
| b0cb6b820b958ea7f92d491bbc8df558a6b7464b |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117684 91177308-0d34-0410-b5e6-96231b3b80d8
eon-convert-encoding.ll
eon-convert-encoding.s
|
| afe18c7cacf94f665a4f00755c41aa2b39d3941e |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117683 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.ll
eon-cmp-encoding.s
|
| 7af3f381ee1b6765bb588bb43e5ac0e3923119bc |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117682 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.ll
eon-bitwise-encoding.s
|
| a007781bdf0e9147165d3b2e5aa21e58c3b7c8b0 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this file to less fragile .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117681 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitcount-encoding.ll
eon-bitcount-encoding.s
|
| 48469e11c90e70b2821f89a516d25f49d0fc8802 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Replace this test with the less fragile .s version. Still XFAIL'd, since the ASM parser doesn't parse vabal yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117679 91177308-0d34-0410-b5e6-96231b3b80d8
eon-absdiff-encoding.ll
eon-absdiff-encoding.s
|
| 14a596258d299d174ebd47cc501cb019b8c99ba0 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Covert this test to a .s file to reduce fragility.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117676 91177308-0d34-0410-b5e6-96231b3b80d8
eon-abs-encoding.ll
eon-abs-encoding.s
|
| 1cfb04390157cdba29216e0bbc2f396124ae14a1 |
29-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Convert this test to a .s file, so that it's not sensitive to codegen changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117633 91177308-0d34-0410-b5e6-96231b3b80d8
g.exp
eon-add-encoding.ll
eon-add-encoding.s
|
| 14b93851cc7611ae6c2000f1c162592ead954420 |
29-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
add simple support for addrmode5 operands, allowing
vldr.64 to work. I have no idea if this is fully right, but
it is in the right direction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117626 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 94074a5e4dc8c8a4338a08a93f9d2d03e1bf0b00 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
most simple arm instructions match correctly now,
it looks like we're not handling [] operands though
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117607 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 4e692ab5eeb6cf49dbb9ec9ade21cd91b081ba10 |
28-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
fix the asmmatcher generator to handle targets with no RegisterPrefix
(like ARM) correctly. With this change, we can now match "bx lr"
because we recognize lr as a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117606 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
|
| 9c3e8e28bd236e95117a25f07d3b466d2db80285 |
28-Oct-2010 |
Evan Cheng <evan.cheng@apple.com> |
Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful.
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117530 91177308-0d34-0410-b5e6-96231b3b80d8
eon-absdiff-encoding.ll
eon-add-encoding.ll
eon-bitwise-encoding.ll
eon-cmp-encoding.ll
eon-minmax-encoding.ll
eon-mul-accum-encoding.ll
eon-mul-encoding.ll
eon-pairwise-encoding.ll
eon-reciprocal-encoding.ll
eon-satshift-encoding.ll
eon-shift-encoding.ll
eon-shiftaccum-encoding.ll
eon-shuffle-encoding.ll
eon-sub-encoding.ll
eon-table-encoding.ll
imple-fp-encoding.ll
|
| cfd0e1f3ae97ac20b92649b4a6c75930b1f8b19e |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vtbl and vtbx.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117513 91177308-0d34-0410-b5e6-96231b3b80d8
eon-table-encoding.ll
|
| 3eff4af42ddbac97807348eadd292ff5f276fe69 |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vext, vtrn, vuzp, and vzip.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117512 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shuffle-encoding.ll
|
| 0bccec368a55e80a2911dcb448cdffabf6bcea98 |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vrev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117502 91177308-0d34-0410-b5e6-96231b3b80d8
eon-reverse-encoding.ll
|
| 498ec20703c89d0c2890b0967791f0f5f2b59a2f |
28-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vcvt, which has its own special immediate encoding
for specifying fractional bits for fixed point conversions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117501 91177308-0d34-0410-b5e6-96231b3b80d8
eon-convert-encoding.ll
|
| d2fbdb7f5c85d2191514953bdba0fae7b788e623 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for the get_lane and set_lane variants of vmov.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117495 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.ll
|
| f587a9352a80bc62d9d521d5051c69d1fefecca7 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vdup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117475 91177308-0d34-0410-b5e6-96231b3b80d8
eon-dup-encoding.ll
|
| 82203218d1d801e5c0bdc33fe6afac2e91939a03 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117469 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mov-encoding.ll
|
| 027c84dd3ea886c89ddebaa4badce74e2e462c7f |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vcls, vclz, and vcnt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117466 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitcount-encoding.ll
|
| df800f1b1ba1f406596301329797e44d4c4dc918 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vneg and vqneg.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117463 91177308-0d34-0410-b5e6-96231b3b80d8
eon-neg-encoding.ll
|
| 633919c79a86e36b26fb62007731341a31f2188d |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vabs and vqabs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117460 91177308-0d34-0410-b5e6-96231b3b80d8
eon-abs-encoding.ll
|
| 0745c389d903bf9d8a8705ff49bea818a6be6c52 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vsli and vsri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117459 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shiftaccum-encoding.ll
|
| dd31ed67e67ffa9c7817d96d69e98c0eab8d1e90 |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vsra and vrsra.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117458 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shiftaccum-encoding.ll
|
| 86ed2324a6d2fa54d22afa96520de9e7c9fba28d |
27-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117411 91177308-0d34-0410-b5e6-96231b3b80d8
eon-satshift-encoding.ll
|
| 632c235a316e38e5d0c6d66498064bc3e391fab1 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117402 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.ll
|
| 6a36ad75a40a5baeb254fc66e26e2f0c9af1a504 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vshll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117399 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.ll
|
| 4ba5d61f2de316d67a73c3536fe146daf9fb7cca |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vshr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117396 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.ll
|
| 3557d00a388585b8827d3e864cb8cd24ee42368a |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vshl, register and immediate forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117394 91177308-0d34-0410-b5e6-96231b3b80d8
eon-shift-encoding.ll
|
| c8cb3535a9828dc8e8ce8587e35ef77c8e8ef2a0 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117385 91177308-0d34-0410-b5e6-96231b3b80d8
eon-reciprocal-encoding.ll
|
| 6915cdab8fbda9fd558d538f1b58b2a4eaa16445 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encodings of vpmin and vpmax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117382 91177308-0d34-0410-b5e6-96231b3b80d8
eon-pairwise-encoding.ll
|
| bc4118bd36d90bf7fba68d6b274afb089f295e98 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encoding for vpadal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117380 91177308-0d34-0410-b5e6-96231b3b80d8
eon-pairwise-encoding.ll
|
| 000e105d0f32db81d8a4913b1f58b78ba0642e3c |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vpadd and vpaddl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117377 91177308-0d34-0410-b5e6-96231b3b80d8
eon-pairwise-encoding.ll
|
| a88ea03bf22ba098f1b7d3471d98f3303dcbd33f |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encodings for vmov and vmvn of immediates.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.ll
eon-mov-encoding.ll
|
| 7c730e77908123a83abcfffe781d368e9b873ce9 |
26-Oct-2010 |
Bob Wilson <bob.wilson@apple.com> |
When the "true" and "false" blocks of a diamond if-conversion are the same,
do not double-count the duplicate instructions by counting once from the
beginning and again from the end. Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end. Radar 8589805.
This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction. That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117333 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
|
| 93ef3fd9c0a7737a26fee867a00de7bcf492a430 |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vmax.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117327 91177308-0d34-0410-b5e6-96231b3b80d8
eon-minmax-encoding.ll
|
| a13067e3661402262c44f8dd15e23cacffc4392d |
26-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vmin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117326 91177308-0d34-0410-b5e6-96231b3b80d8
eon-minmax-encoding.ll
|
| 5258b619667c54d3f07c12031fa0d75595a25527 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for NEON vabal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117315 91177308-0d34-0410-b5e6-96231b3b80d8
eon-absdiff-encoding.ll
|
| 410aebc670ea1ae0412dc2bbe0b4b79f25e53ce0 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vaba.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117309 91177308-0d34-0410-b5e6-96231b3b80d8
eon-absdiff-encoding.ll
eon-bitwise-encoding.ll
|
| 28bae6106f3f591e6f174fe269d261d710cb0062 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Tests for NEON encoding of vabdl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117303 91177308-0d34-0410-b5e6-96231b3b80d8
eon-absdiff-encoding.ll
|
| b7e1d77ff5999ee32e8ea096fe0458d622f83be4 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vabd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117302 91177308-0d34-0410-b5e6-96231b3b80d8
eon-absdiff-encoding.ll
|
| 31e6ed890a5336779fa191a98af1fc0513380180 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117294 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.ll
|
| 4110b4325da839e17dae901996b2263a1c672c87 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vbsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117293 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.ll
|
| 162875a9f3be40bfccc07c29ea4ad19f599b9ee4 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct instruction encodings for vbic, vorn, and vmvn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117282 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.ll
|
| 8c71eff59439708a61a2c65919ccf9c2791d1f1b |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vand, veor, and vorr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117279 91177308-0d34-0410-b5e6-96231b3b80d8
eon-bitwise-encoding.ll
|
| c61ec2a2b0c0f5f64b88b36780b992cfbd4b8f3e |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vtst.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117277 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.ll
|
| d0c5b6170f97aff20dbc1e7f24e56a7cfdcb653c |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add NEON encoding tests for vcgt and vacgt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117276 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.ll
|
| 10c15e5d584d8f9ee44740eca3991a63bb45a90d |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encodings of vcge and vacge.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117274 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.ll
|
| 4fe20bbd668528a82254e4fb9152daa4d30af684 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add a warning about our inability to test the encoding of vceq with immediate zero.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117273 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.ll
|
| a2041f18078e60cdd4f1cf3064c7dd9466c227e6 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vceq.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117270 91177308-0d34-0410-b5e6-96231b3b80d8
eon-cmp-encoding.ll
|
| 8b7ce020c3c471f4ba9caa5cc194cad445cd02c3 |
25-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vsubhn and vrsubhn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117269 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.ll
|
| c052a8c772b1d55e5ed1a34f1750dac20c66c641 |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vqsub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117214 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.ll
|
| 61f34bc4bc52c3ec61dd2c392804e60b65edee47 |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vhsub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117189 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.ll
|
| 48c9f2081d9d26a019ecadde5493f7a094896bc8 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add a CMP test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117187 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 884f22869248db5eab10abd88f556230ab91b51a |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vsubw.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117186 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.ll
|
| 2b6b97c815da7d36666638a37ed646a7be0586cf |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vsubl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117183 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.ll
|
| 313252022d1612faab610e682ea0d03789506934 |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vsub.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117177 91177308-0d34-0410-b5e6-96231b3b80d8
eon-sub-encoding.ll
|
| c9db3314333c34458f6648088cdabbbc96696e9a |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vqdmlsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117173 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.ll
|
| 353f8668b8fff8a5e2cfdbb01dc48ae1104d6804 |
23-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vmlsl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117171 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.ll
|
| 432a8142ef8efc4978ceb8d257a21240e2d29777 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
tidy up.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117166 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| f8da5f5dfa5e847d76bf20d0ec4940e3ca51d275 |
23-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117165 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 458509476bd0f9911965de3b550d3f9c43303b0b |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for the correct encoding of NEON vmls.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117145 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.ll
|
| 9b264972734a96b7956d3ff7ad6d7b5dcf5baf39 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vqdmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117134 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.ll
|
| 385e136dce9f77ad949f54277b33b31c0d1f1588 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add the encoding information for the rest of the ARM mode multiply instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117133 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 92205842ca21952929eef1571a9b5b6c758540e0 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct encodings for NEON vmlal.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117131 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.ll
|
| 18341e9e31b95ff865530e04662f540e2cdf3382 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vmla.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117126 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-accum-encoding.ll
|
| 3870b750e6d8af533926138e670f4643a5953e42 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instuction binary encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117121 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 81faa805ce9f4ec2ff926703671cc76694a925f0 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add testscases for encoding of NEON vdqmull.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117115 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.ll
|
| 9463d0e400d4bac590960ba5593d7850870f7187 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
More ARM multiply instruction encoding information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117108 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 4ceccc4e575b6f51bad18a6c16de1877c756598c |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vmull.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117077 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.ll
|
| 3686046a2cad2e3d62c7fbee9aadae1bf242fa4a |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM binary encodings for MVN variants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117076 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| de5370fcbb332413492c74593e152e7c0c61b8a1 |
22-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encoding of vqdmulh and vqrdmulh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117074 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.ll
|
| 3fea19105d4929ad694f0b6272de31924c9f9f09 |
22-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM Binary encoding information for BFC/BFI instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117072 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 636ad14c8a93f914330bd7340ce56b030f06ab4f |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON vmul encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117069 91177308-0d34-0410-b5e6-96231b3b80d8
eon-mul-encoding.ll
|
| 7eca0e17baeb70da9a272f33e06ac542116aed71 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Rename this test to better reflect its contents.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117067 91177308-0d34-0410-b5e6-96231b3b80d8
eon-add-encoding.ll
eon-fp-encoding.ll
|
| 35ea7a4022af6cce13f1ec642c3d607aae05ed45 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encodings of vaddhn and vraddhn.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117064 91177308-0d34-0410-b5e6-96231b3b80d8
eon-fp-encoding.ll
|
| 4bcb949e18d930765b4f0aabf93cc484dce9d159 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add tests for NEON encodings of vqadd, which was already correctly encoded.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117059 91177308-0d34-0410-b5e6-96231b3b80d8
eon-fp-encoding.ll
|
| 1e93466c3a5556db0bd87755e10e2938c2a43c1f |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct NEON encodings for vhadd and vrhadd.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117047 91177308-0d34-0410-b5e6-96231b3b80d8
eon-fp-encoding.ll
|
| 9d50559bae511cd75ea61efb7189e4b954ab4175 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Add correct encodings for NEON vaddw.s* and vaddw.u*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117040 91177308-0d34-0410-b5e6-96231b3b80d8
eon-fp-encoding.ll
|
| e0e6dc3f4ec31c98f6860c56cad406d3882db428 |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Provide correct NEON encodings for vaddl.u* and vaddl.s*.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117039 91177308-0d34-0410-b5e6-96231b3b80d8
eon-fp-encoding.ll
|
| ba3f88100792b020f69ad1e44ec8c784407435a4 |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Fix whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117002 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
|
| 5b7a825ec5551fd1dff8c9f280cc203da3fdedd9 |
21-Oct-2010 |
Andrew Trick <atrick@apple.com> |
putback r116983 and fix simple-fp-encoding.ll tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116992 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
|
| d7795540d0538fb79e70d0519858d463ac4375af |
21-Oct-2010 |
Owen Anderson <resistor@mac.com> |
Implement correct encodings for NEON vadd, both integer and floating point.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116981 91177308-0d34-0410-b5e6-96231b3b80d8
eon-fp-encoding.ll
|
| 01aabdac44af241a9a70c3d6ef8d5007e3e80ce1 |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for moving a value between two ARM core registers and a doublework
extension register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116970 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
|
| 7d31a169af3c49f54e8dd59bb3a75b37afad890b |
21-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for movement between ARM core registers and single-precision
registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116961 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
|
| 8abe32af38b66bf4577526b23b6af6ec7eb6c155 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
ARM mode encoding information for UBFX and SBFX instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116588 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 53e7dcbd47c6ca34c0cd00c35b09ee5a2be7afe1 |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Simplify test file a bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116540 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 8faff9c759f8d87cfb4f0cb604d1dbc9842ae07b |
15-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add testcase for RRX and ASRS (which effectively tests MOVs, since those
are just forms of that instruction).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116538 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| 1de588df69ceb999dd4680679cc3fe519bf9a124 |
14-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
MOVi16 and MOVT ARM mode encodings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116498 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
|
| bbbdcd453d22258cb4dd217eddf016668fcebf84 |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116471 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
|
| 946a2740a54fe2cd57509999384239101bf5b9df |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for 'fmstat'.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116466 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| 88cf038436a142611424c895c601731ffa7c993f |
14-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
- Add encodings for multiply add/subtract instructions in all their glory.
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116464 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| 67a704de03b7466c3bd696c3d40780d277134d57 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add MC encodings for VCVT* instrunctions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| b35ad41fef5d1edd9495f708fb7eae1a0a94ef9d |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116421 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
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| 24989ecc70ad7bbbfc135fe341484ef4fdeabd09 |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM mode operand encoding information for ADDE/SUBE instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116412 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
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| 6932643a371b7a6dcc0c2b4f3a38b6b18759da87 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VNEG and VSQRT. Also add encodings for VMOV, but not a test
just yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116386 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| 54908dd72b1c6add6f3d074df1b67060e5b57025 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VCVT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116385 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| 89c898f8af3e96db25fe4986b7e7f27663ebe26a |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
arithmetic-with-carry-in instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116384 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
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| 1fc6d8837f03471b815a9312091b9432939b49fc |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add VCMPZ and VABS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116383 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| cd776862544518e215b5af8a294f5026ee844684 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Refactor VCMP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116379 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| 5a1fd8cf68a120e0f4a1e71773422a7d5a284a50 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VNMUL[SD].
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116375 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| caa3d467ab849ebf671441f3adf1ecda715e98fe |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encodings for VDIV and VMUL.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116370 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| c14b80f6d3f93777591fa4619b3f3a2b6f92ffaf |
13-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Be nitpicky and line up the comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116365 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
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| dd3bc112e6545634d9700c777c975f072128a51b |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Add encoding for VSUB and VCMP.
Fear not! I'm going to try a refactoring right now. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116359 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| 6e8bf26342c88940e530cf008ea3fc6be56ec836 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Don't need to specify calling convention. Add 'readnone' to functions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116354 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| 174777bb2b0a1896afb5dc5ff96a91d162d00149 |
13-Oct-2010 |
Bill Wendling <isanbard@gmail.com> |
Encoding for VADDD. Plus a test for the VFP instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116348 91177308-0d34-0410-b5e6-96231b3b80d8
imple-fp-encoding.ll
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| 0de6ab3c43ed2143d661115dddf1480545236c91 |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add encoding information for the remainder of the generic arithmetic
ARM instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116313 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
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| 42fac8ee3bc02e18a5887800e812af762b45b9eb |
12-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
MC machine encoding for simple aritmetic instructions that use a shifted
register operand.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116259 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
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| 56ac907c57fcfddfd650238f03c856a9d55987e5 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Implement a few more binary encoding bits. Still very early stage proof-of-
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.
This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116112 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
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| 0f448b5bf682c16c23c7ec239eb74f08d333e8c1 |
08-Oct-2010 |
Jim Grosbach <grosbach@apple.com> |
Add test file for simple ARM binary encodings with MC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116024 91177308-0d34-0410-b5e6-96231b3b80d8
imple-encoding.ll
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| 9ab044f20b85597cdaed6849dfc2b55af023906a |
02-Oct-2010 |
Chris Lattner <sabre@nondot.org> |
move ARM MC tests up one level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115414 91177308-0d34-0410-b5e6-96231b3b80d8
rm_instructions.s
rm_word_directive.s
g.exp
|