Searched refs:SubIdx (Results 1 - 25 of 38) sorted by relevance

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/external/llvm/lib/Target/ARM/
H A DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx,
49 .addReg(DestReg, getDefRegState(true), SubIdx)
35 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const argument
H A DThumb2RegisterInfo.h35 unsigned DestReg, unsigned SubIdx, int Val,
H A DThumb1RegisterInfo.h41 unsigned DestReg, unsigned SubIdx, int Val,
H A DARMBaseRegisterInfo.h166 unsigned DestReg, unsigned SubIdx,
/external/llvm/lib/CodeGen/
H A DLiveDebugVariables.h40 /// renameRegister - Move any user variables in OldReg to NewReg:SubIdx.
43 /// @param SubIdx If NewReg is a virtual register, SubIdx may indicate a sub-
45 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
H A DPeepholeOptimizer.cpp144 unsigned SrcReg, DstReg, SubIdx; local
145 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx))
159 DstRC = TM->getRegisterInfo()->getSubClassWithSubReg(DstRC, SubIdx);
166 // If UseSrcSubIdx is Set, SubIdx also applies to SrcReg, and only uses of
167 // SrcReg:SubIdx should be replaced.
169 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0;
199 // Only accept uses of SrcReg:SubIdx.
200 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx)
280 .addReg(DstReg, 0, SubIdx);
281 // SubIdx applie
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H A DExpandPostRAPseudos.cpp104 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?");
105 unsigned SubIdx = MI->getOperand(3).getImm(); local
107 assert(SubIdx != 0 && "Invalid index for insert_subreg");
108 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
124 MI->RemoveOperand(3); // SubIdx
H A DMachineCopyPropagation.cpp117 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); local
118 if (!SubIdx)
120 return SubIdx == TRI->getSubRegIndex(SrcDef, Src);
H A DMachineRegisterInfo.cpp80 if (unsigned SubIdx = I.getOperand().getSubReg()) {
82 NewRC = TRI->getMatchingSuperRegClass(NewRC, OpRC, SubIdx);
84 NewRC = TRI->getSubClassWithSubReg(NewRC, SubIdx);
H A DLiveDebugVariables.cpp250 /// renameRegister - Update locations to rewrite OldReg as NewReg:SubIdx.
251 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx,
337 /// renameRegister - Replace all references to OldReg with NewReg:SubIdx.
338 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
718 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx, argument
728 Loc.substVirtReg(NewReg, SubIdx, *TRI);
734 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { argument
745 UV->renameRegister(OldReg, NewReg, SubIdx, TRI);
751 renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx) { argument
753 static_cast<LDVImpl*>(pImpl)->renameRegister(OldReg, NewReg, SubIdx);
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H A DMachineInstr.cpp70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, argument
73 if (SubIdx && getSubReg())
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
76 if (SubIdx)
77 setSubReg(SubIdx);
1297 unsigned SubIdx,
1300 if (SubIdx)
1301 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
1313 MO.substVirtReg(ToReg, SubIdx, RegInf
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H A DTwoAddressInstructionPass.cpp1451 unsigned SubIdx = mi->getOperand(3).getImm(); local
1454 mi->getOperand(0).setSubReg(SubIdx);
1476 unsigned DstReg, unsigned SubIdx,
1483 MO.substVirtReg(DstReg, SubIdx, TRI);
1682 unsigned SubIdx = MI->getOperand(i+1).getImm(); local
1707 MRI->getRegClass(SrcReg), SubIdx)) {
1736 .addReg(DstReg, RegState::Define, SubIdx)
1748 unsigned SubIdx = MI->getOperand(i+1).getImm(); local
1749 UpdateRegSequenceSrcs(SrcReg, DstReg, SubIdx, MRI, *TRI);
1475 UpdateRegSequenceSrcs(unsigned SrcReg, unsigned DstReg, unsigned SubIdx, MachineRegisterInfo *MRI, const TargetRegisterInfo &TRI) argument
H A DMachineVerifier.cpp867 unsigned SubIdx = MO->getSubReg(); local
870 if (SubIdx) {
885 if (SubIdx) {
887 TRI->getSubClassWithSubReg(RC, SubIdx);
891 << " does not support subreg index " << SubIdx << "\n";
897 << " does not fully support subreg index " << SubIdx << "\n";
903 if (SubIdx) {
910 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx);
H A DRegisterCoalescer.cpp159 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
304 "Cannot have a physical SubIdx");
845 unsigned SubIdx) {
850 LDV->renameRegister(SrcReg, DstReg, SubIdx);
860 if (DstInt && !Reads && SubIdx)
870 if (SubIdx && MO.isDef())
876 MO.substVirtReg(DstReg, SubIdx, *TRI);
843 updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx) argument
/external/llvm/lib/MC/
H A DMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx))
/external/llvm/include/llvm/Target/
H A DTargetRegisterInfo.h329 const char *getSubRegIndexName(unsigned SubIdx) const {
330 assert(SubIdx && "This is not a subregister index");
331 return SubRegIndexNames[SubIdx-1];
413 /// Reg so its sub-register of index SubIdx is Reg.
414 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, argument
416 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC);
849 unsigned SubIdx; member in class:llvm::PrintReg
852 : TRI(tri), Reg(reg), SubIdx(subidx) {}
H A DTargetInstrInfo.h112 /// SubIdx.
115 unsigned &SubIdx) const {
183 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
184 /// SubIdx.
187 unsigned DestReg, unsigned SubIdx,
/external/llvm/utils/TableGen/
H A DCodeGenRegisters.h302 // registers have a SubIdx sub-register.
304 getSubClassWithSubReg(CodeGenSubRegIndex *SubIdx) const {
305 return SubClassWithSubReg.lookup(SubIdx);
308 void setSubClassWithSubReg(CodeGenSubRegIndex *SubIdx, argument
310 SubClassWithSubReg[SubIdx] = SubRC;
314 // containing only SubIdx super-registers of this class.
315 void getSuperRegClasses(CodeGenSubRegIndex *SubIdx, BitVector &Out) const;
318 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, argument
320 SuperRegClasses[SubIdx].insert(SuperRC);
H A DCodeGenRegisters.cpp461 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); local
462 if (!SubIdx)
465 NewIdx->addComposite(SI->first, SubIdx);
487 // Topological signature computed from SubIdx, TopoId(SubReg).
924 CodeGenRegisterClass::getSuperRegClasses(CodeGenSubRegIndex *SubIdx, argument
928 FindI = SuperRegClasses.find(SubIdx);
1428 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size();
1429 SubIdx != EndIdx; ++SubIdx) {
1430 const RegUnitSet &SubSet = RegUnitSets[SubIdx];
1629 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local
1662 CodeGenSubRegIndex *SubIdx = SubRegIndices[sri]; local
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/external/llvm/lib/Target/
H A DTargetRegisterInfo.cpp41 if (SubIdx) {
43 OS << ':' << TRI->getSubRegIndexName(SubIdx);
45 OS << ":sub(" << SubIdx << ')'; local
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp429 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
432 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
434 // RC is a sub-class of VRC that supports SubIdx. Try to constrain VReg
439 // VReg has been adjusted. It can be used with SubIdx operands now.
445 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx);
446 assert(RC && "No legal register class for VT supports that SubIdx");
480 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
488 SubIdx == DefSubIdx &&
500 // VReg may not support a SubIdx sub-register, and we may need to
503 VReg = ConstrainForSubReg(VReg, SubIdx,
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H A DInstrEmitter.h81 /// supports SubIdx sub-registers. Emit a copy if that isn't possible.
83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h97 unsigned &SubIdx) const;
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h166 /// SubIdx.
169 unsigned &SubIdx) const;
188 unsigned DestReg, unsigned SubIdx,
/external/llvm/include/llvm/MC/
H A DMCRegisterInfo.h315 /// Reg so its sub-register of index SubIdx is Reg.
316 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx,

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