/external/v8/src/ |
H A D | cpu.h | 45 // CPU 53 class CPU : public AllStatic { class in namespace:v8::internal
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonSubtarget.cpp | 41 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): argument 42 HexagonGenSubtargetInfo(TT, CPU, FS), 43 CPUString(CPU.str()) { 64 // Initialize scheduling itinerary for the specified CPU.
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreSubtarget.cpp | 27 const std::string &CPU, const std::string &FS) 28 : XCoreGenSubtargetInfo(TT, CPU, FS) 26 XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | XCoreTargetMachine.cpp | 24 StringRef CPU, StringRef FS, 28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 29 Subtarget(TT, CPU, FS), 23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/chromium/base/ |
H A D | cpu.cc | 17 CPU::CPU() function in class:base::CPU 82 void CPU::Initialize() { 88 // valid Ids in CPUInfo[0] and the CPU identification string in 89 // the other three array elements. The CPU identification string is 102 // Interpret CPU feature information.
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/external/clang/include/clang/Basic/ |
H A D | TargetOptions.h | 30 /// If given, the name of the target CPU to generate code for. 31 std::string CPU; member in class:clang::TargetOptions
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430Subtarget.cpp | 27 const std::string &CPU, 29 MSP430GenSubtargetInfo(TT, CPU, FS) { 26 MSP430Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | MSP430TargetMachine.cpp | 29 StringRef CPU, 34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 35 Subtarget(TT, CPU, FS), 27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXSubtarget.cpp | 35 NVPTXSubtarget::NVPTXSubtarget(const std::string &TT, const std::string &CPU, argument 37 :NVPTXGenSubtargetInfo(TT, "", FS), // Don't pass CPU to subtarget, 44 // Provide the default CPU if none 48 if (FS.empty() && CPU.empty()) 50 else if (!CPU.empty()) 51 TargetName = CPU;
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/external/llvm/lib/Target/Sparc/ |
H A D | SparcSubtarget.cpp | 26 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, argument 28 SparcGenSubtargetInfo(TT, CPU, FS), 35 std::string CPUName = CPU;
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/external/llvm/lib/Target/ARM/ |
H A D | ARMSubtarget.cpp | 37 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, argument 39 : ARMGenSubtargetInfo(TT, CPU, FS) 76 , CPUString(CPU) 96 // ARM version or CPU and then remove this. 100 // Keep a pointer to static instruction cost data for the specified CPU. 103 // Initialize scheduling itinerary for the specified CPU.
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H A D | ARMTargetMachine.cpp | 41 StringRef CPU, StringRef FS, 45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 46 Subtarget(TT, CPU, FS), 57 StringRef CPU, StringRef FS, 61 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 76 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " 83 StringRef CPU, StringRef FS, 87 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 40 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 56 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument 82 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUSubtarget.cpp | 25 SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU, argument 27 SPUGenSubtargetInfo(TT, CPU, FS), 39 // Initialize scheduling itinerary for the specified CPU.
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H A D | SPUTargetMachine.cpp | 35 StringRef CPU, StringRef FS, 39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 40 Subtarget(TT, CPU, FS), 34 SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/CppBackend/ |
H A D | CPPTargetMachine.h | 26 StringRef CPU, StringRef FS, const TargetOptions &Options, 29 : TargetMachine(T, TT, CPU, FS, Options) {} 25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeSubtarget.cpp | 27 const std::string &CPU, 29 MBlazeGenSubtargetInfo(TT, CPU, FS), 34 std::string CPUName = CPU; 39 // Only use instruction scheduling if the selected CPU has an instruction 40 // itinerary (the default CPU is the only one that doesn't). 42 DEBUG(dbgs() << "CPU " << CPUName << "(" << HasItin << ")\n"); 44 // Initialize scheduling itinerary for the specified CPU. 26 MBlazeSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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H A D | MBlazeTargetMachine.cpp | 36 StringRef CPU, StringRef FS, const TargetOptions &Options, 39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), 40 Subtarget(TT, CPU, FS), 35 MBlazeTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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/external/llvm/lib/Target/Mips/ |
H A D | MipsSubtarget.cpp | 27 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, argument 30 MipsGenSubtargetInfo(TT, CPU, FS), 36 std::string CPUName = CPU; 43 // Initialize scheduling itinerary for the specified CPU.
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/external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
H A D | NVPTXMCTargetDesc.cpp | 47 static MCSubtargetInfo *createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, argument 50 InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCSubtarget.cpp | 29 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, argument 31 : PPCGenSubtargetInfo(TT, CPU, FS) 48 std::string CPUName = CPU; 60 // Initialize scheduling itinerary for the specified CPU.
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
H A D | SparcMCTargetDesc.cpp | 46 static MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, argument 49 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/Target/CellSPU/MCTargetDesc/ |
H A D | SPUMCTargetDesc.cpp | 47 static MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, argument 50 InitSPUMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCTargetDesc.cpp | 48 StringRef CPU, 51 InitHexagonMCSubtargetInfo(X, TT, CPU, FS); 47 createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
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/external/llvm/lib/Target/XCore/MCTargetDesc/ |
H A D | XCoreMCTargetDesc.cpp | 46 static MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, argument 49 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
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/external/llvm/lib/MC/ |
H A D | MCSubtargetInfo.cpp | 23 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, argument 42 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, 47 /// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with 49 uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { argument 51 FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs, 74 MCSubtargetInfo::getSchedModelForCPU(StringRef CPU) const { 86 KV.Key = CPU.data(); 89 if (Found == ProcSchedModel+NumProcs || StringRef(Found->Key) != CPU) { 90 errs() << "'" << CPU 100 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) cons [all...] |