| /external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonSubtarget.cpp | 41 HexagonSubtarget::HexagonSubtarget(StringRef TT, StringRef CPU, StringRef FS): argument
42 HexagonGenSubtargetInfo(TT, CPU, FS),
62 ParseSubtargetFeatures(CPUString, FS);
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| /external/llvm/lib/Target/XCore/ |
| H A D | XCoreSubtarget.cpp | 27 const std::string &CPU, const std::string &FS)
28 : XCoreGenSubtargetInfo(TT, CPU, FS)
26 XCoreSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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| H A D | XCoreTargetMachine.cpp | 24 StringRef CPU, StringRef FS,
28 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
29 Subtarget(TT, CPU, FS),
23 XCoreTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/MSP430/ |
| H A D | MSP430Subtarget.cpp | 28 const std::string &FS) :
29 MSP430GenSubtargetInfo(TT, CPU, FS) {
33 ParseSubtargetFeatures(CPUName, FS);
26 MSP430Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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| H A D | MSP430TargetMachine.cpp | 30 StringRef FS,
34 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
35 Subtarget(TT, CPU, FS),
27 MSP430TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXSubtarget.cpp | 36 const std::string &FS, bool is64Bit)
37 :NVPTXGenSubtargetInfo(TT, "", FS), // Don't pass CPU to subtarget,
47 // Get the TargetName from the FS if available
48 if (FS.empty() && CPU.empty())
35 NVPTXSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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| /external/llvm/lib/Target/Sparc/ |
| H A D | SparcSubtarget.cpp | 27 const std::string &FS, bool is64Bit) :
28 SparcGenSubtargetInfo(TT, CPU, FS),
45 ParseSubtargetFeatures(CPUName, FS);
26 SparcSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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| /external/llvm/lib/Target/ARM/ |
| H A D | ARMSubtarget.cpp | 38 const std::string &FS)
39 : ARMGenSubtargetInfo(TT, CPU, FS)
87 if (!FS.empty()) {
89 ArchFS = ArchFS + "," + FS;
91 ArchFS = FS;
37 ARMSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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| H A D | ARMTargetMachine.cpp | 41 StringRef CPU, StringRef FS,
45 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
46 Subtarget(TT, CPU, FS),
57 StringRef CPU, StringRef FS,
61 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
83 StringRef CPU, StringRef FS,
87 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 ARMBaseTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
56 ARMTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
82 ThumbTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/CellSPU/ |
| H A D | SPUSubtarget.cpp | 26 const std::string &FS) :
27 SPUGenSubtargetInfo(TT, CPU, FS),
37 ParseSubtargetFeatures(default_cpu, FS);
25 SPUSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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| H A D | SPUTargetMachine.cpp | 35 StringRef CPU, StringRef FS,
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 Subtarget(TT, CPU, FS),
34 SPUTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/CppBackend/ |
| H A D | CPPTargetMachine.h | 26 StringRef CPU, StringRef FS, const TargetOptions &Options,
29 : TargetMachine(T, TT, CPU, FS, Options) {}
25 CPPTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/MBlaze/ |
| H A D | MBlazeSubtarget.cpp | 28 const std::string &FS):
29 MBlazeGenSubtargetInfo(TT, CPU, FS),
37 ParseSubtargetFeatures(CPUName, FS);
26 MBlazeSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS) argument
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| H A D | MBlazeTargetMachine.cpp | 36 StringRef CPU, StringRef FS, const TargetOptions &Options,
39 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
40 Subtarget(TT, CPU, FS),
35 MBlazeTargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) argument
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| /external/llvm/lib/Target/Mips/ |
| H A D | MipsSubtarget.cpp | 28 const std::string &FS, bool little,
30 MipsGenSubtargetInfo(TT, CPU, FS),
41 ParseSubtargetFeatures(CPUName, FS);
27 MipsSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool little, Reloc::Model RM) argument
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| /external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
| H A D | NVPTXMCTargetDesc.cpp | 48 StringRef FS) {
50 InitNVPTXMCSubtargetInfo(X, TT, CPU, FS);
47 createNVPTXMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
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| /external/llvm/lib/Target/PowerPC/ |
| H A D | PPCSubtarget.cpp | 30 const std::string &FS, bool is64Bit)
31 : PPCGenSubtargetInfo(TT, CPU, FS)
58 ParseSubtargetFeatures(CPUName, FS);
29 PPCSubtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool is64Bit) argument
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| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| H A D | SparcMCTargetDesc.cpp | 47 StringRef FS) {
49 InitSparcMCSubtargetInfo(X, TT, CPU, FS);
46 createSparcMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
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| /external/llvm/include/llvm/Support/ |
| H A D | Solaris.h | 23 #undef FS macro
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| /external/llvm/lib/Target/CellSPU/MCTargetDesc/ |
| H A D | SPUMCTargetDesc.cpp | 48 StringRef FS) {
50 InitSPUMCSubtargetInfo(X, TT, CPU, FS);
47 createSPUMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCTargetDesc.cpp | 49 StringRef FS) {
51 InitHexagonMCSubtargetInfo(X, TT, CPU, FS);
47 createHexagonMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
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| /external/llvm/lib/Target/XCore/MCTargetDesc/ |
| H A D | XCoreMCTargetDesc.cpp | 47 StringRef FS) {
49 InitXCoreMCSubtargetInfo(X, TT, CPU, FS);
46 createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS) argument
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| /external/clang/lib/Analysis/ |
| H A D | FormatStringParsing.h | 47 bool ParseLengthModifier(FormatSpecifier &FS, const char *&Beg, const char *E,
51 T FS; member in class:clang::analyze_format_string::SpecifierResult
59 : FS(fs), Start(start), Stop(false) {}
66 return FS;
68 const T &getValue() { return FS; }
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| H A D | ScanfFormatString.cpp | 101 ScanfSpecifier FS; local
102 if (ParseArgPosition(H, FS, Start, I, E))
113 FS.setSuppressAssignment(I);
125 FS.setFieldWidth(Amt);
135 if (ParseLengthModifier(FS, I, E, LO, /*scanf=*/true) && I == E) {
181 FS.setConversionSpecifier(CS);
182 if (CS.consumesDataArgument() && !FS.getSuppressAssignment()
183 && !FS.usesPositionalArg())
184 FS.setArgIndex(argIndex++);
191 return !H.HandleInvalidScanfConversionSpecifier(FS, Be
[all...] |
| /external/llvm/lib/MC/ |
| H A D | MCSubtargetInfo.cpp | 23 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS, argument
41 SubtargetFeatures Features(FS);
49 uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) { argument
50 SubtargetFeatures Features(FS);
65 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) { argument
67 FeatureBits = Features.ToggleFeature(FeatureBits, FS,
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