/external/llvm/lib/Target/ARM/ |
H A D | Thumb1RegisterInfo.cpp | 505 unsigned NewOpc = convertToNonSPOpcode(Opcode); variable 506 if (NewOpc != Opcode && FrameReg != ARM::SP) 507 MI.setDesc(TII.get(NewOpc));
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H A D | ARMExpandPseudoInsts.cpp | 944 unsigned NewOpc = ARM::VLDMDIA; local 946 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 975 unsigned NewOpc = ARM::VSTMDIA; local 977 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1006 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : local 1009 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
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H A D | ARMConstantIslandPass.cpp | 1700 unsigned NewOpc = 0; local 1707 NewOpc = ARM::tLEApcrel; 1714 NewOpc = ARM::tLDRpci; 1721 if (!NewOpc) 1734 U.MI->setDesc(TII->get(NewOpc)); 1754 unsigned NewOpc = 0; local 1760 NewOpc = ARM::tB; 1765 NewOpc = ARM::tBcc; 1771 if (NewOpc) { 1776 Br.MI->setDesc(TII->get(NewOpc)); [all...] |
H A D | ARMISelDAGToDAG.cpp | 3008 unsigned NewOpc = ARM::LDREXD; local 3010 NewOpc = ARM::t2LDREXD; 3024 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(), 3094 unsigned NewOpc = ARM::STREXD; local 3096 NewOpc = ARM::t2STREXD; 3098 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
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H A D | ARMLoadStoreOptimizer.cpp | 776 unsigned NewOpc = getUpdatingLSMultipleOpcode(Opcode, Mode); local 777 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) 875 unsigned NewOpc = 0; local 893 NewOpc = getPreIndexedLoadStoreOpcode(Opcode, AddSub); 912 NewOpc = getPostIndexedLoadStoreOpcode(Opcode, AddSub); 930 BuildMI(MBB, MBBI, dl, TII->get(NewOpc)) 939 if (NewOpc == ARM::LDR_PRE_IMM || NewOpc == ARM::LDRB_PRE_IMM) { 941 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), MI->getOperand(0).getReg()) 946 BuildMI(MBB, MBBI, dl, TII->get(NewOpc), M 1072 InsertLDR_STR(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, int Offset, bool isDef, DebugLoc dl, unsigned NewOpc, unsigned Reg, bool RegDeadKill, bool RegUndef, unsigned BaseReg, bool BaseKill, bool BaseUndef, bool OffKill, bool OffUndef, ARMCC::CondCodes Pred, unsigned PredReg, const TargetInstrInfo *TII, bool isT2) argument 1135 unsigned NewOpc = (isLd) local 1158 unsigned NewOpc = (isLd) local 1406 unsigned NewOpc = (isThumb2 ? ARM::t2LDMIA_RET : ARM::LDMIA_RET); local 1560 CanFormLdStDWord(MachineInstr *Op0, MachineInstr *Op1, DebugLoc &dl, unsigned &NewOpc, unsigned &EvenReg, unsigned &OddReg, unsigned &BaseReg, int &Offset, unsigned &PredReg, ARMCC::CondCodes &Pred, bool &isT2) argument 1728 unsigned NewOpc = 0; local [all...] |
H A D | ARMISelLowering.cpp | 2376 unsigned NewOpc = (IntNo == Intrinsic::arm_neon_vmulls) local 2378 return DAG.getNode(NewOpc, Op.getDebugLoc(), Op.getValueType(), 4903 unsigned NewOpc = 0; local 4908 NewOpc = ARMISD::VMULLs; 4913 NewOpc = ARMISD::VMULLu; 4918 NewOpc = ARMISD::VMULLs; 4921 NewOpc = ARMISD::VMULLu; 4925 NewOpc = ARMISD::VMULLu; 4930 if (!NewOpc) { 4949 return DAG.getNode(NewOpc, D 6617 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ? local 6641 unsigned NewOpc; local 6964 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode()); local 8200 unsigned NewOpc = 0; local 8319 unsigned NewOpc = 0; local [all...] |
/external/llvm/lib/Target/Mips/ |
H A D | MipsLongBranch.cpp | 220 unsigned NewOpc = TII->GetOppositeBranchOpc(Br->getOpcode()); local 221 const MCInstrDesc &NewDesc = TII->get(NewOpc);
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/external/llvm/lib/Target/X86/ |
H A D | X86MCInstLower.cpp | 223 static void LowerSubReg32_Op0(MCInst &OutMI, unsigned NewOpc) { argument 224 OutMI.setOpcode(NewOpc); 228 static void LowerUnaryToTwoAddr(MCInst &OutMI, unsigned NewOpc) { argument 229 OutMI.setOpcode(NewOpc);
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H A D | X86InstrInfo.cpp | 3282 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate; 3333 unsigned NewOpc; local 3335 NewOpc = GetCondBranchFromCond(NewCC); 3337 NewOpc = getSETFromCond(NewCC, HasMemoryOperand); 3340 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(), 3347 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc)); 3807 unsigned NewOpc = 0; local 3811 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break; 3812 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break; 3813 case X86::TEST32rr: NewOpc 3868 unsigned NewOpc = 0; local 4107 unsigned NewOpc; local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | MachineLICM.cpp | 1255 unsigned NewOpc = local 1260 if (NewOpc == 0) return 0; 1261 const MCInstrDesc &MID = TII->get(NewOpc);
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H A D | TwoAddressInstructionPass.cpp | 1106 unsigned NewOpc = local 1111 if (NewOpc != 0) { 1112 const MCInstrDesc &UnfoldMCID = TII->get(NewOpc);
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPUISelDAGToDAG.cpp | 608 unsigned NewOpc = 0; local 622 NewOpc = SPU::AIr32; 627 NewOpc = SPU::Ar32; 860 NewOpc = SPU::Ar32; 866 NewOpc = SPU::AIr32; 882 return CurDAG->SelectNodeTo(N, NewOpc, OpVT, Ops, n_ops); 884 return CurDAG->getMachineNode(NewOpc, dl, OpVT, Ops, n_ops);
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H A D | SPUISelLowering.cpp | 743 unsigned NewOpc = ISD::ANY_EXTEND; local 746 NewOpc = ISD::FP_EXTEND; 748 result = DAG.getNode(NewOpc, dl, OutVT, result);
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/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | LegalizeIntegerTypes.cpp | 353 unsigned NewOpc = N->getOpcode(); local 363 NewOpc = ISD::FP_TO_SINT; 365 SDValue Res = DAG.getNode(NewOpc, dl, NVT, N->getOperand(0));
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 6759 unsigned NewOpc; local 6762 case ARM::t2LSLri: NewOpc = ARM::tLSLri; break; 6763 case ARM::t2LSRri: NewOpc = ARM::tLSRri; break; 6764 case ARM::t2ASRri: NewOpc = ARM::tASRri; break; 6768 TmpInst.setOpcode(NewOpc); 7233 unsigned NewOpc; local 7236 case ARM::t2SXTH: NewOpc = ARM::tSXTH; break; 7237 case ARM::t2SXTB: NewOpc = ARM::tSXTB; break; 7238 case ARM::t2UXTH: NewOpc = ARM::tUXTH; break; 7239 case ARM::t2UXTB: NewOpc 7348 unsigned NewOpc; local 7387 unsigned NewOpc; local [all...] |