/external/clang/lib/StaticAnalyzer/Checkers/ |
H A D | ReturnUndefChecker.cpp | 30 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const; 34 void ReturnUndefChecker::checkPreStmt(const ReturnStmt *RS, argument 37 const Expr *RetE = RS->getRetValue();
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H A D | ReturnPointerRangeChecker.cpp | 30 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const; 34 void ReturnPointerRangeChecker::checkPreStmt(const ReturnStmt *RS, argument 38 const Expr *RetE = RS->getRetValue();
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H A D | CheckObjCDealloc.cpp | 207 Selector RS = Ctx.Selectors.getSelector(0, &RII); local 239 if (scan_ivar_release(MD->getBody(), ID, PD, RS, SelfII, Ctx)
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H A D | StackAddrEscapeChecker.cpp | 33 void checkPreStmt(const ReturnStmt *RS, CheckerContext &C) const; 115 void StackAddrEscapeChecker::checkPreStmt(const ReturnStmt *RS, argument 118 const Expr *RetE = RS->getRetValue();
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H A D | MallocChecker.cpp | 691 const RefState *RS = state->get<RegionState>(Sym); local 694 if (RS && (RS->isReleased() || RS->isRelinquished())) { 700 (RS->isReleased() ? "Attempt to free released memory" : 710 ReleasedAllocated = (RS != 0); 1043 RegionStateTy RS = state->get<RegionState>(); local 1048 for (RegionStateTy::iterator I = RS.begin(), E = RS.end(); I != E; ++I) { 1055 RS 1091 RefState RS = I->second; local 1194 const RefState *RS = C.getState()->get<RegionState>(Sym); local 1276 RegionStateTy RS = state->get<RegionState>(); local 1510 const RefState *RS = state->get<RegionState>(Sym); local 1593 RegionStateTy RS = State->get<RegionState>(); local [all...] |
/external/llvm/lib/CodeGen/ |
H A D | PrologEpilogInserter.h | 51 RegScavenger *RS; member in class:llvm::PEI
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H A D | BranchFolding.h | 93 RegScavenger *RS; member in class:llvm::BranchFolder
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H A D | TailDuplication.cpp | 66 OwningPtr<RegScavenger> RS; member in class:__anon8741::TailDuplicatePass 136 RS.reset(); 138 RS.reset(new RegScavenger()); 789 if (RS && !TailBB->livein_empty()) { 791 RS->enterBasicBlock(PredBB); 793 RS->forward(prior(PredBB->end())); 795 RS->getRegsUsed(RegsLiveAtExit, false);
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H A D | MachineVerifier.cpp | 139 bool addPassed(const RegSet &RS) { argument 141 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I) 158 bool addRequired(const RegSet &RS) { argument 160 for (RegSet::const_iterator I = RS.begin(), E = RS.end(); I != E; ++I)
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/external/llvm/lib/Target/CellSPU/ |
H A D | SPURegisterInfo.cpp | 256 RegScavenger *RS) const 300 unsigned tmpReg = findScratchRegister(II, RS, &SPU::R32CRegClass, SPAdj); 347 RegScavenger *RS, 351 assert(RS && "Register scavenging must be on"); 352 unsigned Reg = RS->FindUnusedReg(RC); 354 Reg = RS->scavengeRegister(RC, II, SPAdj); 346 findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, const TargetRegisterClass *RC, int SPAdj) const argument
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/external/clang/lib/StaticAnalyzer/Core/ |
H A D | Environment.cpp | 116 const ReturnStmt *RS = cast<ReturnStmt>(E); local 117 if (const Expr *RE = RS->getRetValue()) {
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H A D | RangeConstraintManager.cpp | 85 RangeSet(PrimRangeSet RS) : ranges(RS) {} argument
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H A D | ExprEngineCallAndReturn.cpp | 151 if (const ReturnStmt *RS = dyn_cast_or_null<ReturnStmt>(LastSt)) { 153 SVal V = state->getSVal(RS, LCtx); 685 void ExprEngine::VisitReturnStmt(const ReturnStmt *RS, ExplodedNode *Pred, argument 689 getCheckerManager().runCheckersForPreStmt(dstPreVisit, Pred, RS, *this); 693 if (RS->getRetValue()) { 696 B.generateNode(RS, *it, (*it)->getState());
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/external/guava/guava/src/com/google/common/base/ |
H A D | Ascii.java | 335 * relationship shall be: FS is the most inclusive, then GS, then RS, 355 public static final byte RS = 30; field in class:Ascii
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/external/llvm/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 535 unsigned RS = getRS(insn); local 672 if (RD == UNSUPPORTED || RS == UNSUPPORTED) 675 instr.addOperand(MCOperand::CreateReg(RS)); 679 if (RS == UNSUPPORTED || RA == UNSUPPORTED) 681 instr.addOperand(MCOperand::CreateReg(RS));
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 262 unsigned findScratchRegister(MachineBasicBlock::iterator II, RegScavenger *RS, argument 264 assert(RS && "Register scavenging must be on"); 265 unsigned Reg = RS->FindUnusedReg(RC); 269 Reg = RS->scavengeRegister(RC, II, SPAdj); 281 int SPAdj, RegScavenger *RS) const { 318 Reg = findScratchRegister(II, RS, RC, SPAdj); 397 RegScavenger *RS) const { 408 (void) RS; 440 RegScavenger *RS) const { 451 (void) RS; [all...] |
/external/dropbear/libtomcrypt/src/ciphers/twofish/ |
H A D | twofish.c | 55 /* The 4x8 RS Linear Transform */ 56 static const unsigned char RS[4][8] = { variable 223 /* computes [y0 y1 y2 y3] = RS . [x0 x1 x2 x3 x4 x5 x6 x7] */ 234 /* computes [y0 y1 y2 y3] = RS . [x0 x1 x2 x3 x4 x5 x6 x7] */ 241 out[x] ^= gf_mult(in[y], RS[x][y], RS_POLY);
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/external/llvm/include/llvm/Support/ |
H A D | IntegersSubsetMapping.h | 219 SuccessorClass *RS) { 229 CurrentRSuccessor = RS; 217 onLROpen(const IntTy &Pt, SuccessorClass *LS, SuccessorClass *RS) argument
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/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonHardwareLoops.cpp | 192 RegScavenger &RS); 584 RegScavenger RS; local 590 RS.enterBasicBlock(MBB); 597 RS.forward(MII); 604 convertLoopInstr(MF, MII, RS); 625 RegScavenger &RS) { 629 unsigned Scratch = RS.scavengeRegister(&Hexagon::IntRegsRegClass, MII, 0); 623 convertLoopInstr(MachineFunction &MF, MachineBasicBlock::iterator &MII, RegScavenger &RS) argument
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/external/clang/lib/Sema/ |
H A D | SemaLambda.cpp | 325 const ReturnStmt *RS = *I; local 326 const Expr *RetE = RS->getRetValue(); 329 Diag(RS->getLocStart(), 346 ReturnStmt *RS = *I; local 347 Expr *RetE = RS->getRetValue(); 357 RS->setRetValue(Casted.take());
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/external/aac/libAACenc/src/ |
H A D | metadata_compressor.cpp | 121 RS = 5, enumerator in enum:__anon107 531 drcComp->channelIdx[RS] = channelMapping.elInfo[2].ChannelIndex[1]; 539 drcComp->channelIdx[RS] = channelMapping.elInfo[2].ChannelIndex[1]; 547 drcComp->channelIdx[RS] = channelMapping.elInfo[2].ChannelIndex[1]; 884 if (drcComp->channelIdx[RS] >= 0) tmp -= fMultDiv2(FL2FXCONST_DBL(0.707f), (FIXP_PCM)pSamples[drcComp->channelIdx[RS]])>>(DOWNMIX_SHIFT-1); /* Rs */ 897 if (drcComp->channelIdx[RS] >= 0) tmp += fMultDiv2(FL2FXCONST_DBL(0.707f), (FIXP_PCM)pSamples[drcComp->channelIdx[RS]])>>(DOWNMIX_SHIFT-1); /* Rs */ 899 if ((drcComp->channelIdx[RS] >= 0) && (drcComp->channelIdx[RS2] >= 0)) tmp = fMult(FL2FXCONST_DBL(0.707f), tmp); /* 7.1ch */ 922 if (drcComp->channelIdx[RS] > [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMLoadStoreOptimizer.cpp | 69 RegScavenger *RS; member in struct:__anon8843::ARMLoadStoreOpt 1045 RS->forward(prior(Loc)); 1231 RS->enterBasicBlock(&MBB); 1325 unsigned Scratch = RS->FindUnusedReg(&ARM::GPRRegClass); 1327 RS->forward(prior(MBBI)); 1348 // RS may be pointing to an instruction that's deleted. 1349 RS->skipTo(prior(MBBI)); 1355 RS->forward(prior(MBBI)); 1425 RS = new RegScavenger(); 1437 delete RS; [all...] |
/external/qemu/tcg/ppc/ |
H A D | tcg-target.c | 396 #define RS(r) ((r)<<21) macro 408 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b)) 453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); 477 tcg_out32 (s, MTSPR | RS (0) | CTR); 502 tcg_out32 (s, MTSPR | RS (arg) | LR); 558 | RS (addr_reg) 573 | RS (addr_reg) 605 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3)); 608 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3)); 672 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_re [all...] |
/external/qemu/tcg/ppc64/ |
H A D | tcg-target.c | 393 #define RS(r) ((r)<<21) macro 406 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b)) 447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb); 457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff)); 477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16); 478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16); 497 tcg_out32 (s, MTSPR | RS (0) | CTR); 509 tcg_out32 (s, MTSPR | RS (arg) | LR); 577 | RS (addr_reg) 587 | RS (addr_re [all...] |
/external/webkit/Source/JavaScriptCore/assembler/ |
H A D | ARMAssembler.h | 437 m_buffer.putInt(static_cast<ARMWord>(cc) | MUL | RN(rd) | RS(rn) | RM(rm)); 442 m_buffer.putInt(static_cast<ARMWord>(cc) | MUL | SET_CC | RN(rd) | RS(rn) | RM(rm)); 447 m_buffer.putInt(static_cast<ARMWord>(cc) | MULL | RN(rdhi) | RD(rdlo) | RS(rn) | RM(rm)); 908 ARMWord RS(int reg) function in class:JSC::ARMAssembler
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