/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXRegisterInfo.h | 73 const char *getName(unsigned RegNo) const { 75 O << "reg" << RegNo; local
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/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmLexer.cpp | 105 int RegNo = -1; local 107 case '0': RegNo = X86::DR0; break; 108 case '1': RegNo = X86::DR1; break; 109 case '2': RegNo = X86::DR2; break; 110 case '3': RegNo = X86::DR3; break; 111 case '4': RegNo = X86::DR4; break; 112 case '5': RegNo = X86::DR5; break; 113 case '6': RegNo = X86::DR6; break; 114 case '7': RegNo = X86::DR7; break; 117 if (RegNo ! [all...] |
H A D | X86AsmParser.cpp | 115 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 181 unsigned RegNo; member in struct:__anon8982::X86Operand::__anon8983::__anon8985 222 return Reg.RegNo; 451 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) { argument 453 Res->Reg.RegNo = RegNo; 521 bool X86AsmParser::ParseRegister(unsigned &RegNo, argument 523 RegNo = 0; 539 RegNo = MatchRegisterName(Tok.getString()); 542 if (RegNo 782 unsigned RegNo = 0; local 799 unsigned RegNo; local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonAsmPrinter.h | 64 unsigned RegNo = MO.getReg(); local 65 assert(TargetRegisterInfo::isPhysicalRegister(RegNo) && "Not physreg??"); 66 O << getRegisterName(RegNo); 156 static const char *getRegisterName(unsigned RegNo);
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/external/llvm/lib/Target/PowerPC/InstPrinter/ |
H A D | PPCInstPrinter.cpp | 26 void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { 27 OS << getRegisterName(RegNo); 92 unsigned RegNo; local 95 case PPC::CR0: RegNo = 0; break; 96 case PPC::CR1: RegNo = 1; break; 97 case PPC::CR2: RegNo = 2; break; 98 case PPC::CR3: RegNo = 3; break; 99 case PPC::CR4: RegNo = 4; break; 100 case PPC::CR5: RegNo = 5; break; 101 case PPC::CR6: RegNo 196 unsigned RegNo; local [all...] |
/external/llvm/lib/MC/MCParser/ |
H A D | COFFAsmParser.cpp | 124 bool ParseSEHRegisterNumber(unsigned &RegNo); 452 bool COFFAsmParser::ParseSEHRegisterNumber(unsigned &RegNo) { argument 478 RegNo = SEHRegNo; 486 RegNo = n;
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H A D | AsmParser.cpp | 2818 unsigned RegNo; local 2821 if (getParser().getTargetParser().ParseRegister(RegNo, DirectiveLoc, 2824 Register = getContext().getRegisterInfo().getDwarfRegNum(RegNo, true);
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
H A D | MipsMCCodeEmitter.cpp | 184 unsigned RegNo = getMipsRegisterNumbering(Reg); local 185 return RegNo;
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/external/llvm/lib/Target/X86/MCTargetDesc/ |
H A D | X86MCTargetDesc.cpp | 214 unsigned X86_MC::getX86RegNum(unsigned RegNo) { argument 215 switch(RegNo) { 248 return RegNo-X86::ST0; 298 assert((int(RegNo) > 0) && "Unknown physical register!");
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H A D | X86BaseInfo.h | 594 inline bool isX86_64ExtendedReg(unsigned RegNo) { argument 595 switch (RegNo) {
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/external/llvm/include/llvm/CodeGen/ |
H A D | CallingConvLower.h | 68 unsigned RegNo, MVT LocVT, 72 Ret.Loc = RegNo; 82 unsigned RegNo, MVT LocVT, 85 Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP); 67 getReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP) argument 81 getCustomReg(unsigned ValNo, MVT ValVT, unsigned RegNo, MVT LocVT, LocInfo HTP) argument
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H A D | MachineInstrBuilder.h | 59 MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0, argument 63 MI->addOperand(MachineOperand::CreateReg(RegNo,
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H A D | MachineOperand.h | 141 unsigned RegNo; // For MO_Register. member in union:llvm::MachineOperand::__anon8445 160 // Register number is in SmallContents.RegNo. 259 return SmallContents.RegNo; 574 Op.SmallContents.RegNo = Reg;
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H A D | MachineRegisterInfo.h | 62 MachineOperand *&getRegUseDefListHead(unsigned RegNo) { argument 63 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 64 return VRegInfo[RegNo].second; 65 return PhysRegUseDefLists[RegNo]; 68 MachineOperand *getRegUseDefListHead(unsigned RegNo) const { 69 if (TargetRegisterInfo::isVirtualRegister(RegNo)) 70 return VRegInfo[RegNo].second; 71 return PhysRegUseDefLists[RegNo]; 170 reg_iterator reg_begin(unsigned RegNo) const { 171 return reg_iterator(getRegUseDefListHead(RegNo)); [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 102 unsigned RegNo, 107 unsigned RegNo, 112 unsigned RegNo, 117 unsigned RegNo, 122 unsigned RegNo, 132 unsigned RegNo, 320 static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) { argument 322 return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo); 326 unsigned RegNo, 330 if (RegNo > 3 325 DecodeCPU64RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 338 DecodeCPURegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 349 DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 361 DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 373 DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 422 DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 442 DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 455 DecodeHWRegs64RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 38 MBlazeOperand *ParseRegister(unsigned &RegNo); 43 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 390 bool MBlazeAsmParser::ParseRegister(unsigned &RegNo, argument 392 return (ParseRegister(RegNo) == 0); 395 MBlazeOperand *MBlazeAsmParser::ParseRegister(unsigned &RegNo) { argument 402 RegNo = MatchRegisterName(getLexer().getTok().getIdentifier()); 403 if (RegNo == 0) 407 return MBlazeOperand::CreateReg(RegNo, S, E); 463 unsigned RegNo; local 464 Op = ParseRegister(RegNo); [all...] |
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCFrameLowering.cpp | 112 unsigned RegNo = getPPCRegisterNumbering(I->first); local 113 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 114 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 119 unsigned RegNo = getPPCRegisterNumbering(*I); local 120 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 121 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
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/external/llvm/utils/TableGen/ |
H A D | RegisterInfoEmitter.cpp | 345 int RegNo = I->second[i]; local 346 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 349 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
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/external/llvm/lib/Target/ARM/MCTargetDesc/ |
H A D | ARMMCCodeEmitter.cpp | 410 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg); local 415 return RegNo; 420 return 2 * RegNo; 1368 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg); 1370 Binary |= (RegNo & 0x1f) << 8; 1377 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg()); 1378 Binary |= 1 << RegNo; 1393 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg()); 1405 return RegNo | (Align << 4); 1416 unsigned RegNo [all...] |
/external/llvm/lib/Target/Mips/AsmParser/ |
H A D | MipsAsmParser.cpp | 48 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 102 unsigned getReg(int RC,int RegNo); 412 unsigned MipsAsmParser::getReg(int RC,int RegNo){ argument 413 return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo); 456 int RegNo = -1; local 461 RegNo = Parser.getTok().getIntVal(); //get the int value 463 if (RegNo == 0) 464 RegNo = Mips::FCC0; 466 RegNo = tryParseRegister(Mnemonic); 467 if (RegNo 628 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) argument 703 int RegNo = op->getReg(); local [all...] |
/external/llvm/lib/CodeGen/AsmPrinter/ |
H A D | AsmPrinter.cpp | 533 unsigned RegNo = MI->getOperand(0).getReg(); local 535 AP.TM.getRegisterInfo()->getName(RegNo));
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 2455 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; local 2456 if (RegNo <= 0) 2463 DefCycle = RegNo / 2 + 1; 2464 if (RegNo % 2) 2467 DefCycle = RegNo; 2481 if ((isSLoad && (RegNo % 2)) || DefAlign < 8) 2485 DefCycle = RegNo + 2; 2496 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; local 2497 if (RegNo <= 0) 2505 DefCycle = RegNo / 2531 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; local 2571 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; local [all...] |
/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 161 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 164 unsigned RegNo, uint64_t Address, 166 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 170 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 172 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 174 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 176 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 179 unsigned RegNo, 182 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 913 DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 924 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 936 DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 943 DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 973 DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 990 DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1011 DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1021 DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1029 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1044 DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1064 DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument 1085 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, const void *Decoder) argument [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 1428 SDValue SelectionDAG::getRegister(unsigned RegNo, EVT VT) { argument 1431 ID.AddInteger(RegNo); 1436 SDNode *N = new (NodeAllocator) RegisterSDNode(RegNo, VT);
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/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 255 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 2453 bool ARMAsmParser::ParseRegister(unsigned &RegNo, argument 2456 RegNo = tryParseRegister(); 2459 return (RegNo == (unsigned)-1); 2619 int RegNo = tryParseRegister(); local 2620 if (RegNo == -1) 2623 Operands.push_back(ARMOperand::CreateReg(RegNo, S, Parser.getTok().getLoc()));
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