/external/clang/test/SemaTemplate/ |
H A D | instantiate-declref.cpp | 41 namespace N2 { namespace 70 template struct N2::Outer2::Inner<float>; 71 template struct N2::Outer2::Inner<int*, float*>; // expected-note{{instantiation}}
|
H A D | instantiate-expr-2.cpp | 13 namespace N2 { namespace 26 one_byte operator+(N1::X, N2::Y); 43 typedef N4::BinOpOverload<N1::X, N2::Y>::type XY; 47 typedef N4::BinOpOverload<N2::Y, N2::Y>::type YY;
|
/external/clang/test/Modules/Inputs/ |
H A D | namespaces-left.h | 9 namespace N2 { namespace
|
/external/flac/libFLAC/ |
H A D | window.c | 99 const double N2 = (double)N / 2.; local 103 double k = ((double)n - N2) / N2; 121 const double N2 = (double)N / 2.; local 125 const double k = ((double)n - N2) / (stddev * N2); 216 const double N2 = (double)N / 2.; local 220 const double k = ((double)n - N2) / N2;
|
/external/openssl/crypto/bn/asm/ |
H A D | ppc64-mont.pl | 152 $N0="f20"; $N1="f21"; $N2="f22"; $N3="f23"; 348 lfd $N2,`$FRAME+112`($sp) 356 fcfid $N2,$N2 375 stfd $N2,56($nap_d) ; save n[j+1] in double format 389 fmadd $T2a,$N2,$na,$T2a 390 fmadd $T2b,$N2,$nb,$T2b 400 fmadd $T3a,$N2,$nc,$T3a 401 fmadd $T3b,$N2,$nd,$T3b 470 lfd $N2,` [all...] |
/external/speex/libspeex/ |
H A D | filters.c | 483 int M2, N2; local 488 N2 = N>>1; 489 ALLOC(xx1, M2+N2, spx_word16_t); 490 ALLOC(xx2, M2+N2, spx_word16_t); 492 for (i = 0; i < N2; i++) 493 xx1[i] = x1[N2-1-i]; 495 xx1[N2+i] = mem1[2*i+1]; 496 for (i = 0; i < N2; i++) 497 xx2[i] = x2[N2-1-i]; 499 xx2[N2 [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 1300 // commuteShuffle - swaps the values of N1 and N2, and swaps all indices in 1301 // the shuffle mask M that point at N1 to point at N2, and indices that point 1302 // N2 to point at N1. 1303 static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { argument 1304 std::swap(N1, N2); 1315 SDValue N2, const int *Mask) { 1316 assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE"); 1323 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) 1336 if (N1 == N2) { 1337 N2 1314 getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2, const int *Mask) argument 1566 FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, DebugLoc dl) argument 2735 getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2) argument 3198 getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3) argument 3288 getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument 3295 getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument 4677 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2) argument 4683 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3) argument 4689 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4) argument 4696 getNode(unsigned Opcode, DebugLoc DL, SDVTList VTList, SDValue N1, SDValue N2, SDValue N3, SDValue N4, SDValue N5) argument [all...] |
H A D | DAGCombiner.cpp | 253 SDValue SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2); 254 SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, 561 SDValue N0, N1, N2; local 562 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) 4036 SDValue N2 = N->getOperand(2); local 4039 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 4044 if (N1 == N2) 4051 return N2; 4054 return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2); 4076 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2); 4120 SDValue N2 = N->getOperand(2); local 5997 SDValue N2 = N->getOperand(2); local 6546 SDValue N2 = N->getOperand(2); local 8494 SimplifySelect(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2) argument 8633 SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2, SDValue N3, ISD::CondCode CC, bool NotExtCompare) argument [all...] |
H A D | InstrEmitter.cpp | 519 SDValue N2 = Node->getOperand(2); 520 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
|
H A D | LegalizeDAG.cpp | 90 SDValue N1, SDValue N2, 182 SDValue N1, SDValue N2, 191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 181 ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, SDValue N1, SDValue N2, ArrayRef<int> Mask) const argument
|
/external/clang/test/CXX/temp/temp.spec/temp.expl.spec/ |
H A D | examples.cpp | 119 namespace N2 { namespace in namespace:PR9482 124 template<> void N2::X::foo() {}
|
/external/llvm/lib/Target/NVPTX/ |
H A D | NVPTXISelDAGToDAG.cpp | 388 SDValue N2 = N->getOperand(2); local 395 if (SelectDirectAddr(N2, Addr)) { 425 SelectADDRsi64(N2.getNode(), N2, Base, Offset): 426 SelectADDRsi(N2.getNode(), N2, Base, Offset)) { 456 SelectADDRri64(N2.getNode(), N2, Base, Offset): 457 SelectADDRri(N2.getNode(), N2, Bas [all...] |
/external/clang/test/SemaCXX/ |
H A D | overloaded-operator.cpp | 372 namespace N2 { namespace 383 using namespace N2::M;
|
/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 493 SDValue getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2, 554 SDValue getNode(unsigned Opcode, DebugLoc DL, EVT VT, SDValue N1, SDValue N2); 556 SDValue N1, SDValue N2, SDValue N3); 558 SDValue N1, SDValue N2, SDValue N3, SDValue N4); 560 SDValue N1, SDValue N2, SDValue N3, SDValue N4, 576 SDValue N1, SDValue N2); 578 SDValue N1, SDValue N2, SDValue N3); 580 SDValue N1, SDValue N2, SDValue N3, SDValue N4); 582 SDValue N1, SDValue N2, SDValue N3, SDValue N4, 985 SDValue N2, IS [all...] |
H A D | SelectionDAGNodes.h | 1118 ShuffleVectorSDNode(EVT VT, DebugLoc dl, SDValue N1, SDValue N2, argument 1121 InitOperands(Ops, N1, N2);
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430ISelDAGToDAG.cpp | 120 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, 354 SDValue N1, SDValue N2, 367 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() }; 353 SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2, unsigned Opc8, unsigned Opc16) argument
|
/external/clang/test/CodeGenCXX/ |
H A D | references.cpp | 178 namespace N2 { namespace
|
/external/llvm/lib/Target/XCore/ |
H A D | XCoreISelLowering.cpp | 1346 SDValue N2 = N->getOperand(2); local 1353 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); 1358 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, 1370 DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); 1373 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); 1383 SDValue N2 = N->getOperand(2); local 1393 DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); 1395 SDValue Borrow = N2; 1397 DAG.getConstant(0, VT), N2); 1409 DAG.ComputeMaskedBits(N2, KnownZer 1422 SDValue N2 = N->getOperand(2); local [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelDAGToDAG.cpp | 836 SDValue N2 = N->getOperand(2); local 837 if (N000 == N2 && 860 SDValue N2 = N->getOperand(2); local 861 if (N000 == N2 &&
|
/external/llvm/lib/Target/ARM/ |
H A D | ARMISelLowering.cpp | 5001 SDValue N2; local 5013 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 5017 N1, N2); 5018 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); 5023 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); 5044 SDValue N2, N3; local 5050 N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0, 5060 N2 = LowerSDIV_v4i8(N2, N 5079 SDValue N2, N3; local 7052 SDValue N2 = N->getOperand(2); local [all...] |
H A D | ARMISelDAGToDAG.cpp | 2585 SDValue N2 = N0.getOperand(1); local 2586 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); 2700 SDValue N2 = N->getOperand(2); local 2704 assert(N2.getOpcode() == ISD::Constant); 2708 cast<ConstantSDNode>(N2)->getZExtValue()),
|
/external/llvm/lib/Target/X86/ |
H A D | X86ISelDAGToDAG.cpp | 2619 SDValue N2 = Node->getOperand(2); local 2635 SDValue Ops[] = { N0, N2, getI8Imm(Imm), InFlag }; 2662 SDValue N2 = Node->getOperand(2); local 2665 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N2);
|
H A D | X86ISelLowering.cpp | 7082 SDValue N2 = Op.getOperand(2); local 7088 isa<ConstantSDNode>(N2)) { 7101 if (N2.getValueType() != MVT::i32) 7102 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7103 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7106 if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7115 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7118 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7136 SDValue N2 = Op.getOperand(2); local [all...] |
/external/llvm/utils/TableGen/ |
H A D | CodeGenDAGPatterns.cpp | 1963 TreePatternNode *N1 = Nodes[i], *N2 = Nodes[i+1]; local 1964 assert(N1->getNumTypes() == 1 && N2->getNumTypes() == 1 && 1967 MadeChange |= N1->UpdateNodeType(0, N2->getExtType(0), *this); 1968 MadeChange |= N2->UpdateNodeType(0, N1->getExtType(0), *this);
|
/external/antlr/antlr-3.4/runtime/Delphi/Sources/Antlr3.Runtime/ |
H A D | Antlr.Runtime.Tree.pas | 4136 I, N1, N2: Integer; 4151 N2 := Adaptor.GetChildCount(T2); 4152 if (N1 <> N2) then 4190 I, N1, N2: Integer; 4213 N2 := T2.ChildCount; 4214 if (N1 <> N2) then
|