/external/llvm/lib/Target/ARM/ |
H A D | ARMInstrInfo.cpp | 37 NopInst.addOperand(MCOperand::CreateReg(0)); 40 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); 41 NopInst.addOperand(MCOperand::CreateReg(ARM::R0)); 43 NopInst.addOperand(MCOperand::CreateReg(0)); 44 NopInst.addOperand(MCOperand::CreateReg(0));
|
H A D | ARMAsmPrinter.cpp | 1037 BrInst.addOperand(MCOperand::CreateReg(0)); 1087 Inst.addOperand(MCOperand::CreateReg(Dest)); 1091 Inst.addOperand(MCOperand::CreateReg(ccreg)); 1312 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1313 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC)); 1316 TmpInst.addOperand(MCOperand::CreateReg(0)); 1318 TmpInst.addOperand(MCOperand::CreateReg(0)); 1324 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); 1333 TmpInst.addOperand(MCOperand::CreateReg(ARM::LR)); 1334 TmpInst.addOperand(MCOperand::CreateReg(AR [all...] |
H A D | Thumb1InstrInfo.cpp | 31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8)); 34 NopInst.addOperand(MCOperand::CreateReg(0));
|
H A D | ARMMCInstLower.cpp | 75 MCOp = MCOperand::CreateReg(MO.getReg());
|
H A D | Thumb2ITBlockPass.cpp | 185 MI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/, 210 NMI->addOperand(MachineOperand::CreateReg(ARM::ITSTATE, false/*ifDef*/,
|
H A D | Thumb2InstrInfo.cpp | 40 NopInst.addOperand(MCOperand::CreateReg(0)); 432 MI.addOperand(MachineOperand::CreateReg(0, false)); 463 MI.addOperand(MachineOperand::CreateReg(0, false));
|
/external/llvm/lib/Target/X86/Disassembler/ |
H A D | X86Disassembler.cpp | 174 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum)); 385 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4))); 388 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4))); 451 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break; 496 baseReg = MCOperand::CreateReg(X86::x); break; 501 baseReg = MCOperand::CreateReg(0); 542 indexReg = MCOperand::CreateReg(X86::x); break; 550 indexReg = MCOperand::CreateReg(0); 567 baseReg = MCOperand::CreateReg(X86::RIP); // Section 2.2.1.6 570 baseReg = MCOperand::CreateReg( [all...] |
/external/llvm/lib/Target/MBlaze/Disassembler/ |
H A D | MBlazeDisassembler.cpp | 548 instr.addOperand(MCOperand::CreateReg(RD)); 549 instr.addOperand(MCOperand::CreateReg(RB)); 550 instr.addOperand(MCOperand::CreateReg(RA)); 556 instr.addOperand(MCOperand::CreateReg(RD)); 557 instr.addOperand(MCOperand::CreateReg(RA)); 558 instr.addOperand(MCOperand::CreateReg(RB)); 564 instr.addOperand(MCOperand::CreateReg(RD)); 565 instr.addOperand(MCOperand::CreateReg(RA)); 575 instr.addOperand(MCOperand::CreateReg(RD)); 582 instr.addOperand(MCOperand::CreateReg(R [all...] |
/external/llvm/lib/Target/Mips/Disassembler/ |
H A D | MipsDisassembler.cpp | 334 Inst.addOperand(MCOperand::CreateReg(Reg)); 345 Inst.addOperand(MCOperand::CreateReg(Reg)); 357 Inst.addOperand(MCOperand::CreateReg(Reg)); 369 Inst.addOperand(MCOperand::CreateReg(Reg)); 377 Inst.addOperand(MCOperand::CreateReg(RegNo)); 393 Inst.addOperand(MCOperand::CreateReg(Reg)); 396 Inst.addOperand(MCOperand::CreateReg(Reg)); 397 Inst.addOperand(MCOperand::CreateReg(Base)); 414 Inst.addOperand(MCOperand::CreateReg(Reg)); 415 Inst.addOperand(MCOperand::CreateReg(Bas [all...] |
/external/llvm/lib/Target/X86/AsmParser/ |
H A D | X86AsmParser.cpp | 383 Inst.addOperand(MCOperand::CreateReg(getReg())); 427 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg())); 429 Inst.addOperand(MCOperand::CreateReg(getMemIndexReg())); 431 Inst.addOperand(MCOperand::CreateReg(getMemSegReg())); 451 static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) { function in struct:__anon8982::X86Operand 785 return X86Operand::CreateReg(RegNo, Start, End); 811 return X86Operand::CreateReg(RegNo, Start, End); 1127 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); 1140 Operands.begin()[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc); 1296 TmpInst.addOperand(MCOperand::CreateReg(X8 [all...] |
/external/llvm/lib/Target/X86/ |
H A D | X86InstrBuilder.h | 64 MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false, 72 MO.push_back(MachineOperand::CreateReg(IndexReg, false, false, 80 MO.push_back(MachineOperand::CreateReg(0, false, false,
|
H A D | X86MCInstLower.cpp | 321 MCOp = MCOperand::CreateReg(MO.getReg()); 538 OutMI.addOperand(MCOperand::CreateReg(X86::R10)); 539 OutMI.addOperand(MCOperand::CreateReg(X86::RAX)); 587 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // dest 588 LEA.addOperand(MCOperand::CreateReg(X86::RIP)); // base 590 LEA.addOperand(MCOperand::CreateReg(0)); // index 592 LEA.addOperand(MCOperand::CreateReg(0)); // seg 595 LEA.addOperand(MCOperand::CreateReg(X86::EAX)); // dest 596 LEA.addOperand(MCOperand::CreateReg(X86::EBX)); // base 598 LEA.addOperand(MCOperand::CreateReg( [all...] |
/external/llvm/lib/Target/ARM/AsmParser/ |
H A D | ARMAsmParser.cpp | 1410 Inst.addOperand(MCOperand::CreateReg(RegNum)); 1440 Inst.addOperand(MCOperand::CreateReg(getReg())); 1445 Inst.addOperand(MCOperand::CreateReg(getReg())); 1452 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg)); 1453 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg)); 1462 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg)); 1480 Inst.addOperand(MCOperand::CreateReg(*I)); 1645 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1674 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum)); 1693 Inst.addOperand(MCOperand::CreateReg(Memor 2126 static ARMOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { function [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonMCInstLower.cpp | 56 MCO = MCOperand::CreateReg(MO.getReg());
|
H A D | HexagonPeephole.cpp | 200 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc, false)); 207 MI->addOperand(MachineOperand::CreateReg(PeepholeSrc.first,
|
/external/llvm/lib/Target/MBlaze/AsmParser/ |
H A D | MBlazeAsmParser.cpp | 193 Inst.addOperand(MCOperand::CreateReg(getReg())); 209 Inst.addOperand(MCOperand::CreateReg(getMemBase())); 213 Inst.addOperand(MCOperand::CreateReg(RegOff)); 234 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { function in struct:__anon8910::MBlazeOperand 407 return MBlazeOperand::CreateReg(RegNo, S, E);
|
/external/llvm/lib/Target/MSP430/ |
H A D | MSP430MCInstLower.cpp | 123 MCOp = MCOperand::CreateReg(MO.getReg());
|
/external/llvm/lib/Target/ARM/Disassembler/ |
H A D | ARMDisassembler.cpp | 643 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 648 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 710 MI.insert(I, MCOperand::CreateReg(0)); 712 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 720 MI.insert(I, MCOperand::CreateReg(0)); 722 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 919 Inst.addOperand(MCOperand::CreateReg(Register)); 969 Inst.addOperand(MCOperand::CreateReg(Register)); 996 Inst.addOperand(MCOperand::CreateReg(Register)); 1017 Inst.addOperand(MCOperand::CreateReg(Registe [all...] |
/external/llvm/include/llvm/CodeGen/ |
H A D | FunctionLoweringInfo.h | 139 unsigned CreateReg(EVT VT);
|
/external/llvm/include/llvm/MC/ |
H A D | MCInst.h | 111 static MCOperand CreateReg(unsigned Reg) { function in class:llvm::MCOperand
|
/external/llvm/lib/Target/MBlaze/ |
H A D | MBlazeMCInstLower.cpp | 127 MCOp = MCOperand::CreateReg(MO.getReg());
|
/external/llvm/lib/Target/Mips/ |
H A D | MipsMCInstLower.cpp | 134 return MCOperand::CreateReg(MO.getReg());
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | InstrEmitter.cpp | 225 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 240 MI->addOperand(MachineOperand::CreateReg(Reg, true)); 252 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 348 MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef, 376 MI->addOperand(MachineOperand::CreateReg(R->getReg(), false, Imp)); 545 MI->addOperand(MachineOperand::CreateReg(VRBase, true)); 928 MI->addOperand(MachineOperand::CreateReg(Reg, true, 936 MI->addOperand(MachineOperand::CreateReg(Reg, /*isDef=*/ true,
|
/external/llvm/lib/CodeGen/ |
H A D | LiveVariables.cpp | 247 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, 270 LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, 383 PhysRegDef[Reg]->addOperand(MachineOperand::CreateReg(SubReg, 400 LastPartDef->addOperand(MachineOperand::CreateReg(Reg, false/*IsDef*/, 643 Ret->addOperand(MachineOperand::CreateReg(*I, false, true));
|
/external/llvm/lib/Target/NVPTX/ |
H A D | VectorElementize.cpp | 264 copy->addOperand(MachineOperand::CreateReg(scalarRegs[i], true)); 300 copy->addOperand(MachineOperand::CreateReg(scalarRegs[i], false)); 339 copy->addOperand(MachineOperand::CreateReg(src1[elem], false)); 341 copy->addOperand(MachineOperand::CreateReg(src2[elem], false)); 364 copy->addOperand(MachineOperand::CreateReg(src[which.getImm()], false)); 396 copy->addOperand(MachineOperand::CreateReg(src[i], false)); 460 copy->addOperand(MachineOperand::CreateReg(scalarRegs[i], true)); 533 copy->addOperand(MachineOperand::CreateReg(scalarRegs[i], isDef[j]));
|