Searched refs:NewMIs (Results 1 - 10 of 10) sorted by relevance
/external/llvm/lib/Target/PowerPC/ |
H A D | PPCInstrInfo.cpp | 447 SmallVectorImpl<MachineInstr*> &NewMIs) const{ 451 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 459 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR), PPC::R11)); 460 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) 467 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 475 NewMIs.push_back(BuildMI(MF, DL, get(PPC::MFLR8), PPC::X11)); 476 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) 482 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) 487 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) 494 NewMIs 593 SmallVector<MachineInstr*, 4> NewMIs; local 728 SmallVector<MachineInstr*, 4> NewMIs; local [all...] |
H A D | PPCInstrInfo.h | 74 SmallVectorImpl<MachineInstr*> &NewMIs) const; 78 SmallVectorImpl<MachineInstr*> &NewMIs) const;
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/external/llvm/lib/CodeGen/ |
H A D | TwoAddressInstructionPass.cpp | 1120 SmallVector<MachineInstr *, 2> NewMIs; local 1123 NewMIs)) { 1127 assert(NewMIs.size() == 2 && 1130 NewMIs[1]->addRegisterKilled(Reg, TRI); 1134 mbbi->insert(mi, NewMIs[0]); 1135 mbbi->insert(mi, NewMIs[1]); 1137 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] 1138 << "2addr: NEW INST: " << *NewMIs[1]); local 1141 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); 1142 unsigned NewSrcIdx = NewMIs[ [all...] |
H A D | MachineLICM.cpp | 1268 SmallVector<MachineInstr *, 2> NewMIs; local 1272 NewMIs); 1277 assert(NewMIs.size() == 2 && 1281 MBB->insert(Pos, NewMIs[0]); 1282 MBB->insert(Pos, NewMIs[1]); 1285 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { 1286 NewMIs[0]->eraseFromParent(); 1287 NewMIs[1]->eraseFromParent(); 1292 UpdateRegPressure(NewMIs[ [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonInstrInfo.h | 83 SmallVectorImpl<MachineInstr*> &NewMIs) const; 94 SmallVectorImpl<MachineInstr*> &NewMIs) const;
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H A D | HexagonInstrInfo.cpp | 392 SmallVectorImpl<MachineInstr*> &NewMIs) const 432 SmallVectorImpl<MachineInstr*> &NewMIs) const {
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/external/llvm/lib/Target/X86/ |
H A D | X86InstrInfo.h | 245 SmallVectorImpl<MachineInstr*> &NewMIs) const; 258 SmallVectorImpl<MachineInstr*> &NewMIs) const; 297 SmallVectorImpl<MachineInstr*> &NewMIs) const;
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H A D | X86InstrInfo.cpp | 2958 SmallVectorImpl<MachineInstr*> &NewMIs) const { 2969 NewMIs.push_back(MIB); 2992 SmallVectorImpl<MachineInstr*> &NewMIs) const { 3002 NewMIs.push_back(MIB); 4015 SmallVectorImpl<MachineInstr*> &NewMIs) const { 4062 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); 4066 MachineOperand &MO = NewMIs[0]->getOperand(i); 4123 NewMIs.push_back(DataMI); 4132 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
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/external/llvm/include/llvm/Target/ |
H A D | TargetInstrInfo.h | 579 SmallVectorImpl<MachineInstr*> &NewMIs) const{
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/external/llvm/lib/Target/ARM/ |
H A D | ARMBaseInstrInfo.cpp | 204 std::vector<MachineInstr*> NewMIs; local 214 NewMIs.push_back(MemMI); 215 NewMIs.push_back(UpdateMI); 227 NewMIs.push_back(UpdateMI); 228 NewMIs.push_back(MemMI); 247 MachineInstr *NewMI = NewMIs[j]; 260 MFI->insert(MBBI, NewMIs[1]); 261 MFI->insert(MBBI, NewMIs[0]); 262 return NewMIs[0];
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