Searched refs:isStoreToStackSlot (Results 1 - 23 of 23) sorted by relevance

/external/llvm/lib/Target/CellSPU/
H A DSPUInstrInfo.h44 unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DSPUInstrInfo.cpp98 SPUInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:SPUInstrInfo
/external/llvm/lib/Target/Mips/
H A DMips16InstrInfo.h38 /// isStoreToStackSlot - If the specified machine instruction is a direct
43 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DMipsSEInstrInfo.h39 /// isStoreToStackSlot - If the specified machine instruction is a direct
44 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DMips16InstrInfo.cpp46 /// isStoreToStackSlot - If the specified machine instruction is a direct
52 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const function in class:Mips16InstrInfo
H A DMipsSEInstrInfo.cpp61 /// isStoreToStackSlot - If the specified machine instruction is a direct
67 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const function in class:MipsSEInstrInfo
/external/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.h57 /// isStoreToStackSlot - If the specified machine instruction is a direct
62 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DSparcInstrInfo.cpp54 /// isStoreToStackSlot - If the specified machine instruction is a direct
59 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:SparcInstrInfo
/external/llvm/lib/Target/XCore/
H A DXCoreInstrInfo.h44 /// isStoreToStackSlot - If the specified machine instruction is a direct
49 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DXCoreInstrInfo.cpp72 /// isStoreToStackSlot - If the specified machine instruction is a direct
78 XCoreInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:XCoreInstrInfo
/external/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h100 unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DPPCInstrInfo.cpp118 unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:PPCInstrInfo
/external/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.h48 /// isStoreToStackSlot - If the specified machine instruction is a direct
53 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DHexagonInstrInfo.cpp89 /// isStoreToStackSlot - If the specified machine instruction is a direct
94 unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:HexagonInstrInfo
/external/llvm/lib/Target/MBlaze/
H A DMBlazeInstrInfo.h189 /// isStoreToStackSlot - If the specified machine instruction is a direct
194 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DMBlazeInstrInfo.cpp57 /// isStoreToStackSlot - If the specified machine instruction is a direct
63 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { function in class:MBlazeInstrInfo
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.h102 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
H A DARMBaseInstrInfo.cpp874 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:ARMBaseInstrInfo
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.h178 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
H A DX86InstrInfo.cpp1476 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI, function in class:X86InstrInfo
1489 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
/external/llvm/lib/CodeGen/
H A DInlineSpiller.cpp252 if (SnipLI.reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
782 if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) {
984 InstrReg = TII.isStoreToStackSlot(MI, FI);
H A DStackSlotColoring.cpp367 if (!(StoreReg = TII->isStoreToStackSlot(NextMI, SecondSS))) continue;
/external/llvm/include/llvm/Target/
H A DTargetInstrInfo.h150 /// isStoreToStackSlot - If the specified machine instruction is a direct
155 virtual unsigned isStoreToStackSlot(const MachineInstr *MI, function in class:llvm::TargetInstrInfo
171 /// reference. If not, return false. Unlike isStoreToStackSlot,

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